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authorBill Wendling <isanbard@gmail.com>2013-06-07 21:04:35 +0000
committerBill Wendling <isanbard@gmail.com>2013-06-07 21:04:35 +0000
commite488b4ecdc6bf9a4a2d53f9311827f92c9044db1 (patch)
tree9911bf5f6c41d1a9d6de05c906072a9769e848b2 /lib/Target/XCore/XCoreInstrInfo.cpp
parenta5e5ba611f787f518fd3f7349343f8c4ae863fc2 (diff)
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Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183572 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreInstrInfo.cpp')
-rw-r--r--lib/Target/XCore/XCoreInstrInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp
index e457e0dbf0..eb7a936add 100644
--- a/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -41,7 +41,7 @@ using namespace llvm;
XCoreInstrInfo::XCoreInstrInfo()
: XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
- RI(*this) {
+ RI() {
}
static bool isZeroImm(const MachineOperand &op) {