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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-15 23:28:14 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-15 23:28:14 +0000 |
| commit | f28987b76e758b5f2fcc2c5d2c8e073df54ca91e (patch) | |
| tree | 8f60dc5b88bbfc1192d2a780d9a5ee6702535e5f /lib/Target/XCore/XCoreRegisterInfo.td | |
| parent | f14bacc862eb69c7c779858746cc020386ce5590 (diff) | |
| download | llvm-f28987b76e758b5f2fcc2c5d2c8e073df54ca91e.tar.gz llvm-f28987b76e758b5f2fcc2c5d2c8e073df54ca91e.tar.bz2 llvm-f28987b76e758b5f2fcc2c5d2c8e073df54ca91e.tar.xz | |
Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.
I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreRegisterInfo.td')
| -rw-r--r-- | lib/Target/XCore/XCoreRegisterInfo.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/XCore/XCoreRegisterInfo.td b/lib/Target/XCore/XCoreRegisterInfo.td index 09510976dd..c3542304a4 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.td +++ b/lib/Target/XCore/XCoreRegisterInfo.td @@ -44,13 +44,13 @@ def LR : Ri<15, "lr">, DwarfRegNum<[15]>; // def GRRegs : RegisterClass<"XCore", [i32], 32, // Return values and arguments - [R0, R1, R2, R3, + (add R0, R1, R2, R3, // Not preserved across procedure calls R11, // Callee save - R4, R5, R6, R7, R8, R9, R10]>; + R4, R5, R6, R7, R8, R9, R10)>; // Reserved -def RRegs : RegisterClass<"XCore", [i32], 32, [CP, DP, SP, LR]> { +def RRegs : RegisterClass<"XCore", [i32], 32, (add CP, DP, SP, LR)> { let isAllocatable = 0; } |