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| author | Daniel Dunbar <daniel@zuster.org> | 2012-02-28 15:36:07 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2012-02-28 15:36:07 +0000 |
| commit | 20bd5296cec8d8d597ab9db2aca7346a88e580c8 (patch) | |
| tree | 5ef20ff8f6ec87dd9f39553b8e0f8ad0463280e2 /lib/Target/XCore | |
| parent | ed1242184cabdd3357f035da9ad30ba4c08ff50a (diff) | |
| download | llvm-20bd5296cec8d8d597ab9db2aca7346a88e580c8.tar.gz llvm-20bd5296cec8d8d597ab9db2aca7346a88e580c8.tar.bz2 llvm-20bd5296cec8d8d597ab9db2aca7346a88e580c8.tar.xz | |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore')
| -rw-r--r-- | lib/Target/XCore/XCoreISelLowering.cpp | 10 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreISelLowering.h | 5 |
2 files changed, 8 insertions, 7 deletions
diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index c2d2a5d593..99b1bdd990 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -487,8 +487,8 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG) const { std::pair<SDValue, SDValue> CallResult = LowerCallTo(Chain, IntPtrTy, false, false, - false, false, 0, CallingConv::C, /*isTailCall=*/false, - /*doesNotRet=*/false, /*isReturnValueUsed=*/true, + false, false, 0, CallingConv::C, false, + /*isReturnValueUsed=*/true, DAG.getExternalSymbol("__misaligned_load", getPointerTy()), Args, DAG, DL); @@ -549,8 +549,8 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG) const std::pair<SDValue, SDValue> CallResult = LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), false, false, - false, false, 0, CallingConv::C, /*isTailCall=*/false, - /*doesNotRet=*/false, /*isReturnValueUsed=*/true, + false, false, 0, CallingConv::C, false, + /*isReturnValueUsed=*/true, DAG.getExternalSymbol("__misaligned_store", getPointerTy()), Args, DAG, dl); @@ -875,7 +875,7 @@ LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { SDValue XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, - bool doesNotRet, bool &isTailCall, + bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h index f5a6822dfa..d6c5b329a0 100644 --- a/lib/Target/XCore/XCoreISelLowering.h +++ b/lib/Target/XCore/XCoreISelLowering.h @@ -175,8 +175,9 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals) const; virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, - bool isVarArg, bool doesNotRet, bool &isTailCall, + LowerCall(SDValue Chain, SDValue Callee, + CallingConv::ID CallConv, bool isVarArg, + bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, |