summaryrefslogtreecommitdiff
path: root/lib/Target/XCore
diff options
context:
space:
mode:
authorRichard Osborne <richard@xmos.com>2013-02-17 22:32:41 +0000
committerRichard Osborne <richard@xmos.com>2013-02-17 22:32:41 +0000
commit763c858edeb76173ee4ef5ab9bf7d750db5d8c4f (patch)
tree737b594237e940eeaccbddf6ece0babfff498b2f /lib/Target/XCore
parenta970dde9060d8994c242bd186bb3636d2caf22d2 (diff)
downloadllvm-763c858edeb76173ee4ef5ab9bf7d750db5d8c4f.tar.gz
llvm-763c858edeb76173ee4ef5ab9bf7d750db5d8c4f.tar.bz2
llvm-763c858edeb76173ee4ef5ab9bf7d750db5d8c4f.tar.xz
[XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore')
-rw-r--r--lib/Target/XCore/Disassembler/XCoreDisassembler.cpp21
-rw-r--r--lib/Target/XCore/XCoreInstrFormats.td8
-rw-r--r--lib/Target/XCore/XCoreInstrInfo.td6
3 files changed, 34 insertions, 1 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
index c995a9c345..0bae15c014 100644
--- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
+++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
@@ -140,6 +140,11 @@ static DecodeStatus Decode3RInstruction(MCInst &Inst,
uint64_t Address,
const void *Decoder);
+static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@@ -313,6 +318,9 @@ Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
case 0x16:
Inst.setOpcode(XCore::EQ_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+ case 0x17:
+ Inst.setOpcode(XCore::TSETR_3r);
+ return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
case 0x18:
Inst.setOpcode(XCore::LSS_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
@@ -516,6 +524,19 @@ Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
}
static DecodeStatus
+Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder) {
+ unsigned Op1, Op2, Op3;
+ DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
+ if (S == MCDisassembler::Success) {
+ Inst.addOperand(MCOperand::CreateImm(Op1));
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+ }
+ return S;
+}
+
+static DecodeStatus
Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
diff --git a/lib/Target/XCore/XCoreInstrFormats.td b/lib/Target/XCore/XCoreInstrFormats.td
index 8dceb30b0d..057721e4fa 100644
--- a/lib/Target/XCore/XCoreInstrFormats.td
+++ b/lib/Target/XCore/XCoreInstrFormats.td
@@ -39,6 +39,14 @@ class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
let DecoderMethod = "Decode3RInstruction";
}
+// 3R with first operand as an immediate. Used for TSETR where the first
+// operand is treated as an immediate since it refers to a register number in
+// another thread.
+class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
+ : _F3R<opc, outs, ins, asmstr, pattern> {
+ let DecoderMethod = "Decode3RImmInstruction";
+}
+
class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-27} = opc{8-4};
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td
index 38e2fbc1db..d366919504 100644
--- a/lib/Target/XCore/XCoreInstrInfo.td
+++ b/lib/Target/XCore/XCoreInstrInfo.td
@@ -395,7 +395,11 @@ def STW_2rus : _F2RUS<0b0000, (outs),
defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
-// TODO tsetr
+
+// The first operand is treated as an immediate since it refers to a register
+// number in another thread.
+def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c),
+ "set t[$c]:r$a, $b", []>;
// Three operand long
def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),