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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2007-05-02 08:46:03 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2007-05-02 08:46:03 +0000 |
| commit | 038082d96652601c70a98d4edffc834c835fc0bf (patch) | |
| tree | ba6ad14efebc791cabe0eec0c18f19f5b0d3bfc8 /lib/Target | |
| parent | d60a18dfbc33b33ab07146641b72fbd33c25d69c (diff) | |
| download | llvm-038082d96652601c70a98d4edffc834c835fc0bf.tar.gz llvm-038082d96652601c70a98d4edffc834c835fc0bf.tar.bz2 llvm-038082d96652601c70a98d4edffc834c835fc0bf.tar.xz | |
Emit correct DWARF reg # for RA (return address) register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36646 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 3 |
2 files changed, 7 insertions, 1 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index e5f57ca24e..4795319a28 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -1235,7 +1235,10 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, } unsigned X86RegisterInfo::getRARegister() const { - return X86::ST0; // use a non-register register + if (Is64Bit) + return X86::RIP; // Should have dwarf #16 + else + return X86::EIP; // Should have dwarf #8 } unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const { diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index 7727a67416..089078a3ae 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -60,6 +60,7 @@ let Namespace = "X86" in { def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<5>; def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<6>; def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<7>; + def IP : Register<"IP">, DwarfRegNum<8>; // X86-64 only def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<8>; @@ -80,6 +81,7 @@ let Namespace = "X86" in { def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<5>; def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<6>; def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<7>; + def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<8>; // X86-64 only def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<8>; @@ -109,6 +111,7 @@ let Namespace = "X86" in { def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<13>; def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<14>; def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<15>; + def RIP : RegisterWithSubRegs<"RIP", [EIP]>, DwarfRegNum<16>; // MMX Registers. These are actually aliased to ST0 .. ST7 def MM0 : Register<"MM0">, DwarfRegNum<29>; |