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| author | Jack Carter <jcarter@mips.com> | 2013-01-16 00:07:45 +0000 |
|---|---|---|
| committer | Jack Carter <jcarter@mips.com> | 2013-01-16 00:07:45 +0000 |
| commit | 490c7d97737ea7719efcea7321d3cfa3984b0027 (patch) | |
| tree | de5ee01765ee31806f32f574d1ac4c7264a10bdf /lib/Target | |
| parent | 72f7bfbf0e02bb11d3e7cca1f9598c5f9d9fa2ca (diff) | |
| download | llvm-490c7d97737ea7719efcea7321d3cfa3984b0027.tar.gz llvm-490c7d97737ea7719efcea7321d3cfa3984b0027.tar.bz2 llvm-490c7d97737ea7719efcea7321d3cfa3984b0027.tar.xz | |
Akira,
Hope you are feeling better.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 16 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 2 |
3 files changed, 21 insertions, 2 deletions
diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 57338df53c..482210673a 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1071,6 +1071,9 @@ MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { + + if (!isMips64()) + return MatchOperand_NoMatch; //if the first token is not '$' we have error if (Parser.getTok().isNot(AsmToken::Dollar)) return MatchOperand_NoMatch; @@ -1088,7 +1091,7 @@ MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S, Parser.getTok().getLoc()); - op->setRegKind(MipsOperand::Kind_HWRegs); + op->setRegKind(MipsOperand::Kind_HW64Regs); Operands.push_back(op); Parser.Lex(); // Eat reg number diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 1efeffd328..9560f3fc52 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -128,6 +128,11 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -454,6 +459,17 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) { + //Currently only hardware register 29 is supported + if (RegNo != 29) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index c6eb0e1e87..f93dd86c17 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -373,6 +373,6 @@ def HWRegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> { let ParserMatchClass = HWRegsAsmOperand; } -def HW64RegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> { +def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> { let ParserMatchClass = HW64RegsAsmOperand; } |