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| author | Reed Kotler <rkotler@mips.com> | 2013-08-07 04:00:26 +0000 |
|---|---|---|
| committer | Reed Kotler <rkotler@mips.com> | 2013-08-07 04:00:26 +0000 |
| commit | 51c9043f3bc215bb3026486e5e1ef5989a8d8d8b (patch) | |
| tree | 9e0343687f36f8fdd107c77400982e09858e01f7 /lib/Target | |
| parent | 9286ee62920806fc695fc3be23b51b73cb707cb5 (diff) | |
| download | llvm-51c9043f3bc215bb3026486e5e1ef5989a8d8d8b.tar.gz llvm-51c9043f3bc215bb3026486e5e1ef5989a8d8d8b.tar.bz2 llvm-51c9043f3bc215bb3026486e5e1ef5989a8d8d8b.tar.xz | |
Create a pattern for the "trap" instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187863 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/Mips/Mips16InstrFormats.td | 14 | ||||
| -rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 15 |
2 files changed, 29 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips16InstrFormats.td b/lib/Target/Mips/Mips16InstrFormats.td index 1e49934980..da3a1f114a 100644 --- a/lib/Target/Mips/Mips16InstrFormats.td +++ b/lib/Target/Mips/Mips16InstrFormats.td @@ -148,6 +148,20 @@ class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr, let Inst{4-0} = funct; } +class FRRBreak16<dag outs, dag ins, string asmstr, + list<dag> pattern, InstrItinClass itin>: + MipsInst16<outs, ins, asmstr, pattern, itin> +{ + bits<6> Code; + bits<5> funct; + + let Opcode = 0b11101; + let funct = 0b00101; + + let Inst{10-5} = Code; + let Inst{4-0} = funct; +} + // // For conversion functions. // diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 0edd225fba..aef4e9283e 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -292,6 +292,11 @@ class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : !strconcat(asmstr, "\t$rx, $ry"), [], itin> { } +class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> : + FRRBreak16<(outs), (ins), asmstr, [], itin> { + let Code=0; +} + class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> : FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), !strconcat(asmstr, "\t$rx, $ry"), [], itin> { @@ -574,6 +579,13 @@ def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; // def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; + +// +//Format: BREAK immediate +// Purpose: Breakpoint +// To cause a Breakpoint exception. + +def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>; // // Format: BTEQZ offset MIPS16e // Purpose: Branch on T Equal to Zero (Extended) @@ -1796,3 +1808,6 @@ def : Mips16Pat<(i32 (extloadi8 addr16:$src)), (LbuRxRyOffMemX16 addr16:$src)>; def : Mips16Pat<(i32 (extloadi16 addr16:$src)), (LhuRxRyOffMemX16 addr16:$src)>; + +def: Mips16Pat<(trap), (Break16)>; + |