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author | Craig Topper <craig.topper@gmail.com> | 2011-10-23 22:18:24 +0000 |
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committer | Craig Topper <craig.topper@gmail.com> | 2011-10-23 22:18:24 +0000 |
commit | 5679ec3b528fb897739251b1f66037767ce2f208 (patch) | |
tree | b4a08c3df8c7e3888821ff987483ce2b83b56e82 /lib/Target | |
parent | 14edd314af99ccaad194d071f23e437a1371f176 (diff) | |
download | llvm-5679ec3b528fb897739251b1f66037767ce2f208.tar.gz llvm-5679ec3b528fb897739251b1f66037767ce2f208.tar.bz2 llvm-5679ec3b528fb897739251b1f66037767ce2f208.tar.xz |
Add X86 SARX, SHRX, and SHLX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142779 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/X86/X86InstrShiftRotate.td | 50 |
1 files changed, 32 insertions, 18 deletions
diff --git a/lib/Target/X86/X86InstrShiftRotate.td b/lib/Target/X86/X86InstrShiftRotate.td index a32f0665d3..58cf6e39c4 100644 --- a/lib/Target/X86/X86InstrShiftRotate.td +++ b/lib/Target/X86/X86InstrShiftRotate.td @@ -744,24 +744,38 @@ def SHRD64mri8 : RIi8<0xAC, MRMDestMem, } // Defs = [EFLAGS] -let Predicates = [HasBMI2], neverHasSideEffects = 1 in { - def RORX32ri : Ii8<0xF0, MRMSrcReg, (outs GR32:$dst), - (ins GR32:$src1, i8imm:$src2), - "rorx{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, - TAXD, VEX; +multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> { +let neverHasSideEffects = 1 in { + def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + []>, TAXD, VEX; let mayLoad = 1 in - def RORX32mi : Ii8<0xF0, MRMSrcMem, (outs GR32:$dst), - (ins i32mem:$src1, i8imm:$src2), - "rorx{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, - TAXD, VEX; - - def RORX64ri : Ii8<0xF0, MRMSrcReg, (outs GR64:$dst), - (ins GR64:$src1, i8imm:$src2), - "rorx{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, - TAXD, VEX, VEX_W; + def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst), + (ins x86memop:$src1, i8imm:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + []>, TAXD, VEX; +} +} + +multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> { +let neverHasSideEffects = 1 in { + def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, + VEX_4VOp3; let mayLoad = 1 in - def RORX64mi : Ii8<0xF0, MRMSrcMem, (outs GR64:$dst), - (ins i64mem:$src1, i8imm:$src2), - "rorx{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, - TAXD, VEX, VEX_W; + def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, + VEX_4VOp3; +} +} + +let Predicates = [HasBMI2] in { + defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>; + defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W; + defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS; + defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W; + defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD; + defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W; + defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8, OpSize; + defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8, OpSize, VEX_W; } |