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author | Jim Grosbach <grosbach@apple.com> | 2011-03-11 23:24:15 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2011-03-11 23:24:15 +0000 |
commit | 72422d38ba6fb2fb0bb9c0c75fe450b3e939ea21 (patch) | |
tree | 7ffd3bcd46c8fedabb8c1cc7748785be647b1dc4 /lib/Target | |
parent | 3c5edaaf59dc051c6d540dd1041cf6bbbb12854f (diff) | |
download | llvm-72422d38ba6fb2fb0bb9c0c75fe450b3e939ea21.tar.gz llvm-72422d38ba6fb2fb0bb9c0c75fe450b3e939ea21.tar.bz2 llvm-72422d38ba6fb2fb0bb9c0c75fe450b3e939ea21.tar.xz |
Pseudo-ize the ARM 'B' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127510 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMAsmPrinter.cpp | 11 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 10 |
2 files changed, 14 insertions, 7 deletions
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 478c246838..b48fbf6740 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -945,6 +945,17 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { unsigned Opc = MI->getOpcode(); switch (Opc) { default: break; + case ARM::B: { + // B is just a Bcc with an 'always' predicate. + MCInst TmpInst; + LowerARMMachineInstrToMCInst(MI, TmpInst, *this); + TmpInst.setOpcode(ARM::Bcc); + // Add predicate operands. + TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); + TmpInst.addOperand(MCOperand::CreateReg(0)); + OutStreamer.EmitInstruction(TmpInst); + return; + } case ARM::LDMIA_RET: { // LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as // such has additional code-gen properties and scheduling information. diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index bb40e39903..7d499749bf 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1485,15 +1485,11 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { } let isBranch = 1, isTerminator = 1 in { - // B is "predicable" since it can be xformed into a Bcc. + // B is "predicable" since it's just a Bcc with an 'always' condition. let isBarrier = 1 in { let isPredicable = 1 in - def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br, - "b\t$target", [(br bb:$target)]> { - bits<24> target; - let Inst{31-28} = 0b1110; - let Inst{23-0} = target; - } + def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br, + [(br bb:$target)]>; let isNotDuplicable = 1, isIndirectBranch = 1 in { def BR_JTr : ARMPseudoInst<(outs), |