diff options
author | Evan Cheng <evan.cheng@apple.com> | 2011-06-27 18:32:37 +0000 |
---|---|---|
committer | Evan Cheng <evan.cheng@apple.com> | 2011-06-27 18:32:37 +0000 |
commit | 73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42 (patch) | |
tree | 2fbec79bd4724de8e90eec820cb0f789b03d203e /lib/Target | |
parent | 4ef4c171dba8e479f5f3fe7acb22e9fe97a4d6f8 (diff) | |
download | llvm-73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42.tar.gz llvm-73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42.tar.bz2 llvm-73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42.tar.xz |
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
68 files changed, 130 insertions, 121 deletions
diff --git a/lib/Target/ARM/ARMBaseInfo.h b/lib/Target/ARM/ARMBaseInfo.h index 36edbad7a6..91e9fd1f9b 100644 --- a/lib/Target/ARM/ARMBaseInfo.h +++ b/lib/Target/ARM/ARMBaseInfo.h @@ -25,7 +25,8 @@ // Defines symbolic names for ARM registers. This defines a mapping from // register name to register number. // -#include "ARMGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "ARMGenRegisterInfo.inc" // Defines symbolic names for the ARM instructions. // diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 0e74ac0cf1..92c98da695 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -39,7 +39,9 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/CommandLine.h" -#include "ARMGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "ARMGenRegisterInfo.inc" using namespace llvm; diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h index 70b6f01d6c..b4b4059e73 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -16,7 +16,9 @@ #include "ARM.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "ARMGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "ARMGenRegisterInfo.inc" namespace llvm { class ARMSubtarget; diff --git a/lib/Target/ARM/CMakeLists.txt b/lib/Target/ARM/CMakeLists.txt index 6cb9689515..0a0ed3c741 100644 --- a/lib/Target/ARM/CMakeLists.txt +++ b/lib/Target/ARM/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS ARM.td) -tablegen(ARMGenRegisterNames.inc -gen-register-enums) -tablegen(ARMGenRegisterDesc.inc -gen-register-desc) -tablegen(ARMGenRegisterInfo.h.inc -gen-register-info-header) tablegen(ARMGenRegisterInfo.inc -gen-register-info) tablegen(ARMGenInstrNames.inc -gen-instr-enums) tablegen(ARMGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/ARM/Makefile b/lib/Target/ARM/Makefile index 0a425143dc..9ecbd6b1b1 100644 --- a/lib/Target/ARM/Makefile +++ b/lib/Target/ARM/Makefile @@ -12,8 +12,7 @@ LIBRARYNAME = LLVMARMCodeGen TARGET = ARM # Make sure that tblgen is run, first thing. -BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \ - ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \ +BUILT_SOURCES = ARMGenRegisterInfo.inc \ ARMGenInstrNames.inc ARMGenInstrInfo.inc \ ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \ ARMGenDAGISel.inc ARMGenSubtarget.inc \ diff --git a/lib/Target/Alpha/Alpha.h b/lib/Target/Alpha/Alpha.h index 2c359dade2..174d2613a9 100644 --- a/lib/Target/Alpha/Alpha.h +++ b/lib/Target/Alpha/Alpha.h @@ -44,7 +44,9 @@ namespace llvm { // Defines symbolic names for Alpha registers. This defines a mapping from // register name to register number. // -#include "AlphaGenRegisterNames.inc" + +#define GET_REGINFO_ENUM +#include "AlphaGenRegisterInfo.inc" // Defines symbolic names for the Alpha instructions. // diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 5ff846eca7..3eef05f751 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -33,8 +33,11 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include <cstdlib> -#include "AlphaGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "AlphaGenRegisterInfo.inc" + using namespace llvm; AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) diff --git a/lib/Target/Alpha/AlphaRegisterInfo.h b/lib/Target/Alpha/AlphaRegisterInfo.h index ffe6cf19e2..1072bf73f1 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.h +++ b/lib/Target/Alpha/AlphaRegisterInfo.h @@ -15,7 +15,9 @@ #define ALPHAREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "AlphaGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "AlphaGenRegisterInfo.inc" namespace llvm { diff --git a/lib/Target/Alpha/CMakeLists.txt b/lib/Target/Alpha/CMakeLists.txt index 1834b06653..bcde447443 100644 --- a/lib/Target/Alpha/CMakeLists.txt +++ b/lib/Target/Alpha/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS Alpha.td) -tablegen(AlphaGenRegisterNames.inc -gen-register-enums) -tablegen(AlphaGenRegisterDesc.inc -gen-register-desc) -tablegen(AlphaGenRegisterInfo.h.inc -gen-register-info-header) tablegen(AlphaGenRegisterInfo.inc -gen-register-info) tablegen(AlphaGenInstrNames.inc -gen-instr-enums) tablegen(AlphaGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/Alpha/Makefile b/lib/Target/Alpha/Makefile index f029793d08..bd280a0e1b 100644 --- a/lib/Target/Alpha/Makefile +++ b/lib/Target/Alpha/Makefile @@ -12,8 +12,7 @@ LIBRARYNAME = LLVMAlphaCodeGen TARGET = Alpha # Make sure that tblgen is run, first thing. -BUILT_SOURCES = AlphaGenRegisterNames.inc AlphaGenRegisterDesc.inc \ - AlphaGenRegisterInfo.h.inc AlphaGenRegisterInfo.inc \ +BUILT_SOURCES = AlphaGenRegisterInfo.inc \ AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \ AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \ AlphaGenCallingConv.inc AlphaGenSubtarget.inc diff --git a/lib/Target/Blackfin/Blackfin.h b/lib/Target/Blackfin/Blackfin.h index ec1fa8689d..3285c4f631 100644 --- a/lib/Target/Blackfin/Blackfin.h +++ b/lib/Target/Blackfin/Blackfin.h @@ -30,7 +30,8 @@ namespace llvm { // Defines symbolic names for Blackfin registers. This defines a mapping from // register name to register number. -#include "BlackfinGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "BlackfinGenRegisterInfo.inc" // Defines symbolic names for the Blackfin instructions. #include "BlackfinGenInstrNames.inc" diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp index 6377d8e403..aa4374488d 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp @@ -29,8 +29,11 @@ #include "llvm/Type.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include "BlackfinGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "BlackfinGenRegisterInfo.inc" + using namespace llvm; BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st, diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.h b/lib/Target/Blackfin/BlackfinRegisterInfo.h index 375d277216..86f45c17c6 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.h +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.h @@ -16,7 +16,9 @@ #define BLACKFINREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "BlackfinGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "BlackfinGenRegisterInfo.inc" namespace llvm { diff --git a/lib/Target/Blackfin/CMakeLists.txt b/lib/Target/Blackfin/CMakeLists.txt index 10896c5864..c59b5a311e 100644 --- a/lib/Target/Blackfin/CMakeLists.txt +++ b/lib/Target/Blackfin/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS Blackfin.td) -tablegen(BlackfinGenRegisterNames.inc -gen-register-enums) -tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc) -tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header) tablegen(BlackfinGenRegisterInfo.inc -gen-register-info) tablegen(BlackfinGenInstrNames.inc -gen-instr-enums) tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/Blackfin/Makefile b/lib/Target/Blackfin/Makefile index 8ea1dfb067..c05d27b4cc 100644 --- a/lib/Target/Blackfin/Makefile +++ b/lib/Target/Blackfin/Makefile @@ -12,9 +12,7 @@ LIBRARYNAME = LLVMBlackfinCodeGen TARGET = Blackfin # Make sure that tblgen is run, first thing. -BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \ - BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \ - BlackfinGenInstrNames.inc \ +BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \ BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \ BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \ BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc diff --git a/lib/Target/CellSPU/CMakeLists.txt b/lib/Target/CellSPU/CMakeLists.txt index dc1f7084a5..1cce2c1a6a 100644 --- a/lib/Target/CellSPU/CMakeLists.txt +++ b/lib/Target/CellSPU/CMakeLists.txt @@ -1,11 +1,8 @@ set(LLVM_TARGET_DEFINITIONS SPU.td) tablegen(SPUGenInstrNames.inc -gen-instr-enums) -tablegen(SPUGenRegisterNames.inc -gen-register-enums) tablegen(SPUGenAsmWriter.inc -gen-asm-writer) tablegen(SPUGenCodeEmitter.inc -gen-emitter) -tablegen(SPUGenRegisterDesc.inc -gen-register-desc) -tablegen(SPUGenRegisterInfo.h.inc -gen-register-info-header) tablegen(SPUGenRegisterInfo.inc -gen-register-info) tablegen(SPUGenInstrInfo.inc -gen-instr-desc) tablegen(SPUGenDAGISel.inc -gen-dag-isel) diff --git a/lib/Target/CellSPU/Makefile b/lib/Target/CellSPU/Makefile index de8a9476d1..270bd6b8b3 100644 --- a/lib/Target/CellSPU/Makefile +++ b/lib/Target/CellSPU/Makefile @@ -10,10 +10,8 @@ LEVEL = ../../.. LIBRARYNAME = LLVMCellSPUCodeGen TARGET = SPU -BUILT_SOURCES = SPUGenInstrNames.inc \ +BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterInfo.inc \ SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \ - SPUGenRegisterNames.inc SPUGenRegisterDesc.inc \ - SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \ SPUGenInstrInfo.inc SPUGenDAGISel.inc \ SPUGenSubtarget.inc SPUGenCallingConv.inc diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index 34f3f9b1ad..a84dd5ae89 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -42,7 +42,9 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include <cstdlib> -#include "SPUGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "SPUGenRegisterInfo.inc" using namespace llvm; diff --git a/lib/Target/CellSPU/SPURegisterInfo.h b/lib/Target/CellSPU/SPURegisterInfo.h index 6ecf0f28dd..5e014f8adb 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.h +++ b/lib/Target/CellSPU/SPURegisterInfo.h @@ -16,7 +16,9 @@ #define SPU_REGISTERINFO_H #include "SPU.h" -#include "SPUGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "SPUGenRegisterInfo.inc" namespace llvm { class SPUSubtarget; diff --git a/lib/Target/CellSPU/SPURegisterNames.h b/lib/Target/CellSPU/SPURegisterNames.h index 6c3afdf41f..e557ed340a 100644 --- a/lib/Target/CellSPU/SPURegisterNames.h +++ b/lib/Target/CellSPU/SPURegisterNames.h @@ -13,6 +13,7 @@ // Define symbolic names for Cell registers. This defines a mapping from // register name to register number. // -#include "SPUGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "SPUGenRegisterInfo.inc" #endif diff --git a/lib/Target/MBlaze/CMakeLists.txt b/lib/Target/MBlaze/CMakeLists.txt index 009564e9ab..86d030dfe8 100644 --- a/lib/Target/MBlaze/CMakeLists.txt +++ b/lib/Target/MBlaze/CMakeLists.txt @@ -1,9 +1,6 @@ set(LLVM_TARGET_DEFINITIONS MBlaze.td) -tablegen(MBlazeGenRegisterNames.inc -gen-register-enums) -tablegen(MBlazeGenRegisterDesc.inc -gen-register-desc) tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header) -tablegen(MBlazeGenRegisterInfo.inc -gen-register-info) tablegen(MBlazeGenInstrNames.inc -gen-instr-enums) tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc) tablegen(MBlazeGenCodeEmitter.inc -gen-emitter) diff --git a/lib/Target/MBlaze/MBlaze.h b/lib/Target/MBlaze/MBlaze.h index 00c73f06fe..c6181f70bc 100644 --- a/lib/Target/MBlaze/MBlaze.h +++ b/lib/Target/MBlaze/MBlaze.h @@ -39,7 +39,8 @@ namespace llvm { // Defines symbolic names for MBlaze registers. This defines a mapping from // register name to register number. -#include "MBlazeGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "MBlazeGenRegisterInfo.inc" // Defines symbolic names for the MBlaze instructions. #include "MBlazeGenInstrNames.inc" diff --git a/lib/Target/MBlaze/MBlazeRegisterInfo.cpp b/lib/Target/MBlaze/MBlazeRegisterInfo.cpp index f52c2e1a29..415c83b31a 100644 --- a/lib/Target/MBlaze/MBlazeRegisterInfo.cpp +++ b/lib/Target/MBlaze/MBlazeRegisterInfo.cpp @@ -36,8 +36,11 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include "MBlazeGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "MBlazeGenRegisterInfo.inc" + using namespace llvm; MBlazeRegisterInfo:: diff --git a/lib/Target/MBlaze/MBlazeRegisterInfo.h b/lib/Target/MBlaze/MBlazeRegisterInfo.h index 380783991c..7ebce21d3a 100644 --- a/lib/Target/MBlaze/MBlazeRegisterInfo.h +++ b/lib/Target/MBlaze/MBlazeRegisterInfo.h @@ -17,7 +17,9 @@ #include "MBlaze.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "MBlazeGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "MBlazeGenRegisterInfo.inc" namespace llvm { class MBlazeSubtarget; diff --git a/lib/Target/MBlaze/Makefile b/lib/Target/MBlaze/Makefile index 81fd5f7bba..010885f04b 100644 --- a/lib/Target/MBlaze/Makefile +++ b/lib/Target/MBlaze/Makefile @@ -11,9 +11,7 @@ LIBRARYNAME = LLVMMBlazeCodeGen TARGET = MBlaze # Make sure that tblgen is run, first thing. -BUILT_SOURCES = MBlazeGenRegisterInfo.h.inc MBlazeGenRegisterNames.inc \ - MBlazeGenRegisterInfo.inc MBlazeGenRegisterDesc.inc \ - MBlazeGenInstrNames.inc \ +BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \ MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \ MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \ MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \ diff --git a/lib/Target/MSP430/CMakeLists.txt b/lib/Target/MSP430/CMakeLists.txt index 90752fabdb..bf58fd2e80 100644 --- a/lib/Target/MSP430/CMakeLists.txt +++ b/lib/Target/MSP430/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS MSP430.td) -tablegen(MSP430GenRegisterNames.inc -gen-register-enums) -tablegen(MSP430GenRegisterDesc.inc -gen-register-desc) -tablegen(MSP430GenRegisterInfo.h.inc -gen-register-info-header) tablegen(MSP430GenRegisterInfo.inc -gen-register-info) tablegen(MSP430GenInstrNames.inc -gen-instr-enums) tablegen(MSP430GenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/MSP430/MSP430.h b/lib/Target/MSP430/MSP430.h index e74211807c..2dabe7c0d3 100644 --- a/lib/Target/MSP430/MSP430.h +++ b/lib/Target/MSP430/MSP430.h @@ -47,7 +47,8 @@ namespace llvm { // Defines symbolic names for MSP430 registers. // This defines a mapping from register name to register number. -#include "MSP430GenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "MSP430GenRegisterInfo.inc" // Defines symbolic names for the MSP430 instructions. #include "MSP430GenInstrNames.inc" diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp index 397b7b403f..0a2e93ac08 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.cpp +++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -25,7 +25,9 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/BitVector.h" #include "llvm/Support/ErrorHandling.h" -#include "MSP430GenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "MSP430GenRegisterInfo.inc" using namespace llvm; diff --git a/lib/Target/MSP430/MSP430RegisterInfo.h b/lib/Target/MSP430/MSP430RegisterInfo.h index e82055876f..fb70594ab3 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.h +++ b/lib/Target/MSP430/MSP430RegisterInfo.h @@ -15,7 +15,9 @@ #define LLVM_TARGET_MSP430REGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "MSP430GenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "MSP430GenRegisterInfo.inc" namespace llvm { diff --git a/lib/Target/MSP430/Makefile b/lib/Target/MSP430/Makefile index 8635646d5e..cdbbf0ef53 100644 --- a/lib/Target/MSP430/Makefile +++ b/lib/Target/MSP430/Makefile @@ -12,9 +12,7 @@ LIBRARYNAME = LLVMMSP430CodeGen TARGET = MSP430 # Make sure that tblgen is run, first thing. -BUILT_SOURCES = MSP430GenRegisterInfo.h.inc MSP430GenRegisterNames.inc \ - MSP430GenRegisterInfo.inc MSP430GenRegisterDesc.inc \ - MSP430GenInstrNames.inc \ +BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \ MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \ MSP430GenDAGISel.inc MSP430GenCallingConv.inc \ MSP430GenSubtarget.inc diff --git a/lib/Target/Mips/CMakeLists.txt b/lib/Target/Mips/CMakeLists.txt index f9d953639f..aa51fbf8a5 100644 --- a/lib/Target/Mips/CMakeLists.txt +++ b/lib/Target/Mips/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS Mips.td) -tablegen(MipsGenRegisterNames.inc -gen-register-enums) -tablegen(MipsGenRegisterDesc.inc -gen-register-desc) -tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header) tablegen(MipsGenRegisterInfo.inc -gen-register-info) tablegen(MipsGenInstrNames.inc -gen-instr-enums) tablegen(MipsGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/Mips/Makefile b/lib/Target/Mips/Makefile index d7eab61a72..3f5cfd7f0b 100644 --- a/lib/Target/Mips/Makefile +++ b/lib/Target/Mips/Makefile @@ -12,9 +12,7 @@ LIBRARYNAME = LLVMMipsCodeGen TARGET = Mips # Make sure that tblgen is run, first thing. -BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \ - MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \ - MipsGenInstrNames.inc \ +BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrNames.inc \ MipsGenInstrInfo.inc MipsGenAsmWriter.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ MipsGenSubtarget.inc diff --git a/lib/Target/Mips/Mips.h b/lib/Target/Mips/Mips.h index 76a26a9ba5..d296b36e65 100644 --- a/lib/Target/Mips/Mips.h +++ b/lib/Target/Mips/Mips.h @@ -35,7 +35,8 @@ namespace llvm { // Defines symbolic names for Mips registers. This defines a mapping from // register name to register number. -#include "MipsGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "MipsGenRegisterInfo.inc" // Defines symbolic names for the Mips instructions. #include "MipsGenInstrNames.inc" diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index 6fdcf45e65..2b74f73fd5 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -35,7 +35,9 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include "MipsGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "MipsGenRegisterInfo.inc" using namespace llvm; diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h index 76b0035f16..646369b596 100644 --- a/lib/Target/Mips/MipsRegisterInfo.h +++ b/lib/Target/Mips/MipsRegisterInfo.h @@ -16,7 +16,9 @@ #include "Mips.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "MipsGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "MipsGenRegisterInfo.inc" namespace llvm { class MipsSubtarget; diff --git a/lib/Target/PTX/CMakeLists.txt b/lib/Target/PTX/CMakeLists.txt index 540af72b7c..42b1925e9d 100644 --- a/lib/Target/PTX/CMakeLists.txt +++ b/lib/Target/PTX/CMakeLists.txt @@ -5,10 +5,7 @@ tablegen(PTXGenCallingConv.inc -gen-callingconv) tablegen(PTXGenDAGISel.inc -gen-dag-isel) tablegen(PTXGenInstrInfo.inc -gen-instr-desc) tablegen(PTXGenInstrNames.inc -gen-instr-enums) -tablegen(PTXGenRegisterDesc.inc -gen-register-desc) tablegen(PTXGenRegisterInfo.inc -gen-register-info) -tablegen(PTXGenRegisterInfo.h.inc -gen-register-info-header) -tablegen(PTXGenRegisterNames.inc -gen-register-enums) tablegen(PTXGenSubtarget.inc -gen-subtarget) add_llvm_target(PTXCodeGen diff --git a/lib/Target/PTX/Makefile b/lib/Target/PTX/Makefile index 1e471de320..7c3f318aac 100644 --- a/lib/Target/PTX/Makefile +++ b/lib/Target/PTX/Makefile @@ -17,10 +17,7 @@ BUILT_SOURCES = PTXGenAsmWriter.inc \ PTXGenDAGISel.inc \ PTXGenInstrInfo.inc \ PTXGenInstrNames.inc \ - PTXGenRegisterDesc.inc \ PTXGenRegisterInfo.inc \ - PTXGenRegisterInfo.h.inc \ - PTXGenRegisterNames.inc \ PTXGenSubtarget.inc DIRS = TargetInfo diff --git a/lib/Target/PTX/PTX.h b/lib/Target/PTX/PTX.h index ec2be9291a..345f87a996 100644 --- a/lib/Target/PTX/PTX.h +++ b/lib/Target/PTX/PTX.h @@ -47,7 +47,8 @@ namespace llvm { } // namespace llvm; // Defines symbolic names for PTX registers. -#include "PTXGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "PTXGenRegisterInfo.inc" // Defines symbolic names for the PTX instructions. #include "PTXGenInstrNames.inc" diff --git a/lib/Target/PTX/PTXRegisterInfo.cpp b/lib/Target/PTX/PTXRegisterInfo.cpp index 5673f963f7..06c542444f 100644 --- a/lib/Target/PTX/PTXRegisterInfo.cpp +++ b/lib/Target/PTX/PTXRegisterInfo.cpp @@ -17,11 +17,11 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" -using namespace llvm; - -#include "PTXGenRegisterDesc.inc" +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "PTXGenRegisterInfo.inc" +using namespace llvm; PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM, const TargetInstrInfo &TII) diff --git a/lib/Target/PTX/PTXRegisterInfo.h b/lib/Target/PTX/PTXRegisterInfo.h index 67e8a1b0cf..0b63cb6d45 100644 --- a/lib/Target/PTX/PTXRegisterInfo.h +++ b/lib/Target/PTX/PTXRegisterInfo.h @@ -17,7 +17,8 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/ADT/BitVector.h" -#include "PTXGenRegisterInfo.h.inc" +#define GET_REGINFO_HEADER +#include "PTXGenRegisterInfo.inc" namespace llvm { class PTXTargetMachine; diff --git a/lib/Target/PowerPC/CMakeLists.txt b/lib/Target/PowerPC/CMakeLists.txt index 99caa9944b..ca5daec210 100644 --- a/lib/Target/PowerPC/CMakeLists.txt +++ b/lib/Target/PowerPC/CMakeLists.txt @@ -1,12 +1,9 @@ set(LLVM_TARGET_DEFINITIONS PPC.td) tablegen(PPCGenInstrNames.inc -gen-instr-enums) -tablegen(PPCGenRegisterNames.inc -gen-register-enums) tablegen(PPCGenAsmWriter.inc -gen-asm-writer) tablegen(PPCGenCodeEmitter.inc -gen-emitter) tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter) -tablegen(PPCGenRegisterDesc.inc -gen-register-desc) -tablegen(PPCGenRegisterInfo.h.inc -gen-register-info-header) tablegen(PPCGenRegisterInfo.inc -gen-register-info) tablegen(PPCGenInstrInfo.inc -gen-instr-desc) tablegen(PPCGenDAGISel.inc -gen-dag-isel) diff --git a/lib/Target/PowerPC/Makefile b/lib/Target/PowerPC/Makefile index 3d01792bec..d7a57f9fa2 100644 --- a/lib/Target/PowerPC/Makefile +++ b/lib/Target/PowerPC/Makefile @@ -12,10 +12,8 @@ LIBRARYNAME = LLVMPowerPCCodeGen TARGET = PPC # Make sure that tblgen is run, first thing. -BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \ +BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterInfo.inc \ PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \ - PPCGenRegisterDesc.inc \ - PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \ PPCGenInstrInfo.inc PPCGenDAGISel.inc \ PPCGenSubtarget.inc PPCGenCallingConv.inc \ PPCGenMCCodeEmitter.inc diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h index 92672b5b17..a8ab8f2995 100644 --- a/lib/Target/PowerPC/PPC.h +++ b/lib/Target/PowerPC/PPC.h @@ -84,7 +84,8 @@ namespace llvm { // Defines symbolic names for PowerPC registers. This defines a mapping from // register name to register number. // -#include "PPCGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "PPCGenRegisterInfo.inc" // Defines symbolic names for the PowerPC instructions. // diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 3950517ca1..bd5c722947 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -43,7 +43,9 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include <cstdlib> -#include "PPCGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "PPCGenRegisterInfo.inc" // FIXME (64-bit): Eventually enable by default. diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index 48c25625ea..33fe5ebcf4 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -16,9 +16,11 @@ #define POWERPC32_REGISTERINFO_H #include "PPC.h" -#include "PPCGenRegisterInfo.h.inc" #include <map> +#define GET_REGINFO_HEADER +#include "PPCGenRegisterInfo.inc" + namespace llvm { class PPCSubtarget; class TargetInstrInfo; diff --git a/lib/Target/Sparc/CMakeLists.txt b/lib/Target/Sparc/CMakeLists.txt index 243e889723..1a5b036c7f 100644 --- a/lib/Target/Sparc/CMakeLists.txt +++ b/lib/Target/Sparc/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td) -tablegen(SparcGenRegisterNames.inc -gen-register-enums) -tablegen(SparcGenRegisterDesc.inc -gen-register-desc) -tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header) tablegen(SparcGenRegisterInfo.inc -gen-register-info) tablegen(SparcGenInstrNames.inc -gen-instr-enums) tablegen(SparcGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/Sparc/Makefile b/lib/Target/Sparc/Makefile index af7d9daa3d..4ef1519346 100644 --- a/lib/Target/Sparc/Makefile +++ b/lib/Target/Sparc/Makefile @@ -12,9 +12,7 @@ LIBRARYNAME = LLVMSparcCodeGen TARGET = Sparc # Make sure that tblgen is run, first thing. -BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \ - SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \ - SparcGenInstrNames.inc \ +BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrNames.inc \ SparcGenInstrInfo.inc SparcGenAsmWriter.inc \ SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h index a37920d803..0f03ca3598 100644 --- a/lib/Target/Sparc/Sparc.h +++ b/lib/Target/Sparc/Sparc.h @@ -36,7 +36,8 @@ namespace llvm { // Defines symbolic names for Sparc registers. This defines a mapping from // register name to register number. // -#include "SparcGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "SparcGenRegisterInfo.inc" // Defines symbolic names for the Sparc instructions. // diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index c63f52e958..48ca15b590 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -23,8 +23,11 @@ #include "llvm/Type.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include "SparcGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "SparcGenRegisterInfo.inc" + using namespace llvm; SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h index 56c8068228..ec9e63a686 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.h +++ b/lib/Target/Sparc/SparcRegisterInfo.h @@ -15,7 +15,9 @@ #define SPARCREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "SparcGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "SparcGenRegisterInfo.inc" namespace llvm { diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt index 3e06109a39..5adf5e3161 100644 --- a/lib/Target/SystemZ/CMakeLists.txt +++ b/lib/Target/SystemZ/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS SystemZ.td) -tablegen(SystemZGenRegisterNames.inc -gen-register-enums) -tablegen(SystemZGenRegisterDesc.inc -gen-register-desc) -tablegen(SystemZGenRegisterInfo.h.inc -gen-register-info-header) tablegen(SystemZGenRegisterInfo.inc -gen-register-info) tablegen(SystemZGenInstrNames.inc -gen-instr-enums) tablegen(SystemZGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/SystemZ/Makefile b/lib/Target/SystemZ/Makefile index 24817152fb..4b45615bc4 100644 --- a/lib/Target/SystemZ/Makefile +++ b/lib/Target/SystemZ/Makefile @@ -12,9 +12,7 @@ LIBRARYNAME = LLVMSystemZCodeGen TARGET = SystemZ # Make sure that tblgen is run, first thing. -BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \ - SystemZGenRegisterInfo.inc SystemZGenRegisterDesc.inc \ - SystemZGenInstrNames.inc \ +BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \ SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \ SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc diff --git a/lib/Target/SystemZ/SystemZ.h b/lib/Target/SystemZ/SystemZ.h index ea5240a10c..8bf9fc54e8 100644 --- a/lib/Target/SystemZ/SystemZ.h +++ b/lib/Target/SystemZ/SystemZ.h @@ -53,7 +53,8 @@ namespace llvm { // Defines symbolic names for SystemZ registers. // This defines a mapping from register name to register number. -#include "SystemZGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "SystemZGenRegisterInfo.inc" // Defines symbolic names for the SystemZ instructions. #include "SystemZGenInstrNames.inc" diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/lib/Target/SystemZ/SystemZRegisterInfo.cpp index a587e1c289..b3c76dd235 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -25,8 +25,11 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/BitVector.h" -#include "SystemZGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "SystemZGenRegisterInfo.inc" + using namespace llvm; SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm, diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.h b/lib/Target/SystemZ/SystemZRegisterInfo.h index cd8f20fee6..2e262e1acc 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.h +++ b/lib/Target/SystemZ/SystemZRegisterInfo.h @@ -15,7 +15,9 @@ #define SystemZREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "SystemZGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "SystemZGenRegisterInfo.inc" namespace llvm { diff --git a/lib/Target/X86/CMakeLists.txt b/lib/Target/X86/CMakeLists.txt index 7237ed8778..31d69af890 100644 --- a/lib/Target/X86/CMakeLists.txt +++ b/lib/Target/X86/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS X86.td) -tablegen(X86GenRegisterNames.inc -gen-register-enums) -tablegen(X86GenRegisterDesc.inc -gen-register-desc) -tablegen(X86GenRegisterInfo.h.inc -gen-register-info-header) tablegen(X86GenRegisterInfo.inc -gen-register-info) tablegen(X86GenDisassemblerTables.inc -gen-disassembler) tablegen(X86GenInstrNames.inc -gen-instr-enums) diff --git a/lib/Target/X86/Disassembler/X86Disassembler.cpp b/lib/Target/X86/Disassembler/X86Disassembler.cpp index d8a105e7e9..4a0d2ec727 100644 --- a/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -26,7 +26,8 @@ #include "llvm/Support/MemoryObject.h" #include "llvm/Support/raw_ostream.h" -#include "X86GenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" #include "X86GenEDInfo.inc" using namespace llvm; diff --git a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp index 68247d2f1a..d01a6007f2 100644 --- a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp @@ -27,12 +27,11 @@ using namespace llvm; // Include the auto-generated portion of the assembly writer. +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" #define GET_INSTRUCTION_NAME #define PRINT_ALIAS_INSTR -#include "X86GenRegisterNames.inc" #include "X86GenAsmWriter.inc" -#undef PRINT_ALIAS_INSTR -#undef GET_INSTRUCTION_NAME X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) : MCInstPrinter(MAI) { diff --git a/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp index 8d61745f10..7aa77bdf6f 100644 --- a/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp +++ b/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp @@ -14,7 +14,9 @@ #include "X86TargetDesc.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Target/TargetRegistry.h" -#include "X86GenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#include "X86GenRegisterInfo.inc" using namespace llvm; MCRegisterInfo *createX86MCRegisterInfo() { diff --git a/lib/Target/X86/MCTargetDesc/X86TargetDesc.h b/lib/Target/X86/MCTargetDesc/X86TargetDesc.h index bcf851fb2b..0d876dc953 100644 --- a/lib/Target/X86/MCTargetDesc/X86TargetDesc.h +++ b/lib/Target/X86/MCTargetDesc/X86TargetDesc.h @@ -23,6 +23,7 @@ extern Target TheX86_32Target, TheX86_64Target; // Defines symbolic names for X86 registers. This defines a mapping from // register name to register number. // -#include "X86GenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" #endif diff --git a/lib/Target/X86/Makefile b/lib/Target/X86/Makefile index 2102db7f74..fad83438d0 100644 --- a/lib/Target/X86/Makefile +++ b/lib/Target/X86/Makefile @@ -12,8 +12,7 @@ LIBRARYNAME = LLVMX86CodeGen TARGET = X86 # Make sure that tblgen is run, first thing. -BUILT_SOURCES = X86GenRegisterNames.inc X86GenRegisterDesc.inc \ - X86GenRegisterInfo.h.inc X86GenRegisterInfo.inc \ +BUILT_SOURCES = X86GenRegisterInfo.inc \ X86GenInstrNames.inc X86GenInstrInfo.inc \ X86GenAsmWriter.inc X86GenAsmMatcher.inc \ X86GenAsmWriter1.inc X86GenDAGISel.inc \ diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index c67da21107..48f60f8934 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -39,8 +39,11 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/CommandLine.h" -#include "X86GenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "X86GenRegisterInfo.inc" + using namespace llvm; cl::opt<bool> diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index 9fd6ed512a..0c014a6b78 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -15,7 +15,9 @@ #define X86REGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "X86GenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "X86GenRegisterInfo.inc" namespace llvm { class Type; diff --git a/lib/Target/XCore/CMakeLists.txt b/lib/Target/XCore/CMakeLists.txt index 959e9a1091..f6e7c20c91 100644 --- a/lib/Target/XCore/CMakeLists.txt +++ b/lib/Target/XCore/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS XCore.td) -tablegen(XCoreGenRegisterNames.inc -gen-register-enums) -tablegen(XCoreGenRegisterDesc.inc -gen-register-desc) -tablegen(XCoreGenRegisterInfo.h.inc -gen-register-info-header) tablegen(XCoreGenRegisterInfo.inc -gen-register-info) tablegen(XCoreGenInstrNames.inc -gen-instr-enums) tablegen(XCoreGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/XCore/Makefile b/lib/Target/XCore/Makefile index f67ef517a1..ddc85dd09c 100644 --- a/lib/Target/XCore/Makefile +++ b/lib/Target/XCore/Makefile @@ -12,9 +12,7 @@ LIBRARYNAME = LLVMXCoreCodeGen TARGET = XCore # Make sure that tblgen is run, first thing. -BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \ - XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \ - XCoreGenInstrNames.inc \ +BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \ XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \ XCoreGenDAGISel.inc XCoreGenCallingConv.inc \ XCoreGenSubtarget.inc diff --git a/lib/Target/XCore/XCore.h b/lib/Target/XCore/XCore.h index 8937fbe123..69c343dc2f 100644 --- a/lib/Target/XCore/XCore.h +++ b/lib/Target/XCore/XCore.h @@ -32,7 +32,8 @@ namespace llvm { // Defines symbolic names for XCore registers. This defines a mapping from // register name to register number. // -#include "XCoreGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "XCoreGenRegisterInfo.inc" // Defines symbolic names for the XCore instructions. // diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index 966e33b6db..0c9473efff 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -32,8 +32,11 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "XCoreGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "XCoreGenRegisterInfo.inc" + using namespace llvm; XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii) diff --git a/lib/Target/XCore/XCoreRegisterInfo.h b/lib/Target/XCore/XCoreRegisterInfo.h index 7a9bc9fb87..801d9eba21 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.h +++ b/lib/Target/XCore/XCoreRegisterInfo.h @@ -15,7 +15,9 @@ #define XCOREREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "XCoreGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "XCoreGenRegisterInfo.inc" namespace llvm { |