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authorAkira Hatanaka <ahatanak@gmail.com>2011-09-23 18:28:39 +0000
committerAkira Hatanaka <ahatanak@gmail.com>2011-09-23 18:28:39 +0000
commit792016bc2202d34d0a3d0b5d12985eca5528c24c (patch)
tree1d220064acd1422b096aff6d5fd9c8d154a14449 /lib/Target
parentb1dcff0fe372d6a691f37413a24d5a6564f1a361 (diff)
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Make FGR64RegisterClass available if target is Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140397 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/Mips/MipsISelLowering.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index fbd2f4b846..0c0b9abdd3 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -84,6 +84,7 @@ MipsTargetLowering::
MipsTargetLowering(MipsTargetMachine &TM)
: TargetLowering(TM, new MipsTargetObjectFile()) {
Subtarget = &TM.getSubtarget<MipsSubtarget>();
+ bool HasMips64 = Subtarget->hasMips64();
// Mips does not have i1 type, so use i32 for
// setcc operations results (slt, sgt, ...).
@@ -95,8 +96,12 @@ MipsTargetLowering(MipsTargetMachine &TM)
addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
// When dealing with single precision only, use libcalls
- if (!Subtarget->isSingleFloat())
+ if (!Subtarget->isSingleFloat()) {
+ if (HasMips64)
+ addRegisterClass(MVT::f64, Mips::FGR64RegisterClass);
+ else
addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
+ }
// Load extented operations for i1 types must be promoted
setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);