Do not use typeinfo to identify pass in pass manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36632 91177308-0d34-0410-b5e6-96231b3b80d8

16 files changed, 70 insertions, 16 deletions

diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index 9237228a91..0850d22994 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -128,6 +128,9 @@ namespace {
     ARMFunctionInfo *AFI;
     bool isThumb;
   public:
+    static const int ID;
+    ARMConstantIslands() : MachineFunctionPass((intptr_t)&ID) {}
+
     virtual bool runOnMachineFunction(MachineFunction &Fn);
 
     virtual const char *getPassName() const {
@@ -171,6 +174,7 @@ namespace {
     void dumpBBs();
     void verify(MachineFunction &Fn);
   };
+  const int ARMConstantIslands::ID = 0;
 }
 
 /// verify - check BBOffsets, BBSizes, alignment of islands
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 3f8f35016d..143fa1bbda 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -38,6 +38,9 @@ STATISTIC(NumFSTMGened, "Number of fstm instructions generated");
 
 namespace {
   struct VISIBILITY_HIDDEN ARMLoadStoreOpt : public MachineFunctionPass {
+    static const int ID;
+    ARMLoadStoreOpt() : MachineFunctionPass((intptr_t)&ID) {}
+
     const TargetInstrInfo *TII;
     const MRegisterInfo *MRI;
     ARMFunctionInfo *AFI;
@@ -70,6 +73,7 @@ namespace {
     bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
     bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
   };
+  const int ARMLoadStoreOpt::ID = 0;
 }
 
 /// createARMLoadStoreOptimizationPass - returns an instance of the load / store
diff --git a/lib/Target/Alpha/AlphaBranchSelector.cpp b/lib/Target/Alpha/AlphaBranchSelector.cpp
index 65bacb8a74..f0f70adffe 100644
--- a/lib/Target/Alpha/AlphaBranchSelector.cpp
+++ b/lib/Target/Alpha/AlphaBranchSelector.cpp
@@ -22,6 +22,8 @@ using namespace llvm;
 
 namespace {
   struct VISIBILITY_HIDDEN AlphaBSel : public MachineFunctionPass {
+    static const int ID;
+    AlphaBSel() : MachineFunctionPass((intptr_t)&ID) {}
 
     virtual bool runOnMachineFunction(MachineFunction &Fn);
 
@@ -29,6 +31,7 @@ namespace {
       return "Alpha Branch Selection";
     }
   };
+  const int AlphaBSel::ID = 0;
 }
 
 /// createAlphaBranchSelectionPass - returns an instance of the Branch Selection
diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp
index 15aef8532d..006e57176e 100644
--- a/lib/Target/Alpha/AlphaCodeEmitter.cpp
+++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp
@@ -36,11 +36,12 @@ namespace {
     int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
 
   public:
+    static const int ID;
     explicit AlphaCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
-      : II(0), TM(tm), MCE(mce) {}
+      : MachineFunctionPass((intptr_t)&ID), II(0), TM(tm), MCE(mce) {}
     AlphaCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
                      const AlphaInstrInfo& ii)
-      : II(&ii), TM(tm), MCE(mce) {}
+      : MachineFunctionPass((intptr_t)&ID), II(&ii), TM(tm), MCE(mce) {}
 
     bool runOnMachineFunction(MachineFunction &MF);
 
@@ -60,6 +61,7 @@ namespace {
     void emitBasicBlock(MachineBasicBlock &MBB);
 
   };
+  const int AlphaCodeEmitter::ID = 0;
 }
 
 /// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha code
diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp
index 6d2d243e3d..c5a20e7a0c 100644
--- a/lib/Target/Alpha/AlphaLLRP.cpp
+++ b/lib/Target/Alpha/AlphaLLRP.cpp
@@ -37,7 +37,9 @@ namespace {
     ///
     AlphaTargetMachine &TM;
 
-    AlphaLLRPPass(AlphaTargetMachine &tm) : TM(tm) { }
+    static const int ID;
+    AlphaLLRPPass(AlphaTargetMachine &tm) 
+      : MachineFunctionPass((intptr_t)&ID), TM(tm) { }
 
     virtual const char *getPassName() const {
       return "Alpha NOP inserter";
@@ -152,6 +154,7 @@ namespace {
       return Changed;
     }
   };
+  const int AlphaLLRPPass::ID = 0;
 } // end of anonymous namespace
 
 FunctionPass *llvm::createAlphaLLRPPass(AlphaTargetMachine &tm) {
diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp
index ac7251f898..e29edff13b 100644
--- a/lib/Target/CBackend/CBackend.cpp
+++ b/lib/Target/CBackend/CBackend.cpp
@@ -56,6 +56,10 @@ namespace {
   /// external functions with the same name.
   ///
   class CBackendNameAllUsedStructsAndMergeFunctions : public ModulePass {
+  public:
+    static const int ID;
+    CBackendNameAllUsedStructsAndMergeFunctions() 
+      : ModulePass((intptr_t)&ID) {}
     void getAnalysisUsage(AnalysisUsage &AU) const {
       AU.addRequired<FindUsedTypes>();
     }
@@ -67,6 +71,8 @@ namespace {
     virtual bool runOnModule(Module &M);
   };
 
+  const int CBackendNameAllUsedStructsAndMergeFunctions::ID = 0;
+
   /// CWriter - This class is the main chunk of code that converts an LLVM
   /// module to a C translation unit.
   class CWriter : public FunctionPass, public InstVisitor<CWriter> {
@@ -82,8 +88,10 @@ namespace {
     std::set<Function*> intrinsicPrototypesAlreadyGenerated;
 
   public:
-    CWriter(std::ostream &o) : Out(o), IL(0), Mang(0), LI(0), TheModule(0), 
-                               TAsm(0), TD(0) {}
+    static const int ID;
+    CWriter(std::ostream &o) 
+      : FunctionPass((intptr_t)&ID), Out(o), IL(0), Mang(0), LI(0), 
+        TheModule(0), TAsm(0), TD(0) {}
 
     virtual const char *getPassName() const { return "C backend"; }
 
@@ -256,6 +264,8 @@ namespace {
   };
 }
 
+const int CWriter::ID = 0;
+
 /// This method inserts names for any unnamed structure types that are used by
 /// the program, and removes names from structure types that are not used by the
 /// program.
diff --git a/lib/Target/IA64/IA64Bundling.cpp b/lib/Target/IA64/IA64Bundling.cpp
index 08e4ba8d37..89732aed5f 100644
--- a/lib/Target/IA64/IA64Bundling.cpp
+++ b/lib/Target/IA64/IA64Bundling.cpp
@@ -36,12 +36,14 @@ STATISTIC(StopBitsAdded, "Number of stop bits added");
 
 namespace {
   struct IA64BundlingPass : public MachineFunctionPass {
+    static const int ID;
     /// Target machine description which we query for reg. names, data
     /// layout, etc.
     ///
     IA64TargetMachine &TM;
 
-    IA64BundlingPass(IA64TargetMachine &tm) : TM(tm) { }
+    IA64BundlingPass(IA64TargetMachine &tm) 
+      : MachineFunctionPass((intptr_t)&ID), TM(tm) { }
 
     virtual const char *getPassName() const {
       return "IA64 (Itanium) Bundling Pass";
@@ -61,6 +63,7 @@ namespace {
     // 'fallthrough' code
     std::set<unsigned> PendingRegWrites;
   };
+  const int IA64BundlingPass::ID = 0;
 } // end of anonymous namespace
 
 /// createIA64BundlingPass - Returns a pass that adds STOP (;;) instructions
diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp
index 55eb03c7d0..86bea59db4 100644
--- a/lib/Target/MSIL/MSILWriter.cpp
+++ b/lib/Target/MSIL/MSILWriter.cpp
@@ -80,6 +80,8 @@ bool MSILModule::runOnModule(Module &M) {
   return Changed;
 }
 
+const int MSILModule::ID = 0;
+const int MSILWriter::ID = 0;
 
 bool MSILWriter::runOnFunction(Function &F) {
   if (F.isDeclaration()) return false;
diff --git a/lib/Target/MSIL/MSILWriter.h b/lib/Target/MSIL/MSILWriter.h
index 7fa039e3d9..15a463d73d 100644
--- a/lib/Target/MSIL/MSILWriter.h
+++ b/lib/Target/MSIL/MSILWriter.h
@@ -37,9 +37,10 @@ namespace {
     const TargetData*& TD;
 
   public:
+    static const int ID;
     MSILModule(const std::set<const Type *>*& _UsedTypes,
                const TargetData*& _TD)
-      : UsedTypes(_UsedTypes), TD(_TD) {}
+      : ModulePass((intptr_t)&ID), UsedTypes(_UsedTypes), TD(_TD) {}
 
     void getAnalysisUsage(AnalysisUsage &AU) const {
       AU.addRequired<FindUsedTypes>();
@@ -82,8 +83,8 @@ namespace {
     std::map<const GlobalVariable*,std::vector<StaticInitializer> >
       StaticInitList;
     const std::set<const Type *>* UsedTypes;
-
-    MSILWriter(std::ostream &o) : Out(o) {
+    static const int ID;
+    MSILWriter(std::ostream &o) : FunctionPass((intptr_t)&ID), Out(o) {
       UniqID = 0;
     }
 
diff --git a/lib/Target/PowerPC/PPCBranchSelector.cpp b/lib/Target/PowerPC/PPCBranchSelector.cpp
index 2cd8325ce3..a4f0caee8a 100644
--- a/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ b/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -32,6 +32,9 @@ STATISTIC(NumExpanded, "Number of branches expanded to long format");
 
 namespace {
   struct VISIBILITY_HIDDEN PPCBSel : public MachineFunctionPass {
+    static const int ID;
+    PPCBSel() : MachineFunctionPass((intptr_t)&ID) {}
+
     /// BlockSizes - The sizes of the basic blocks in the function.
     std::vector<unsigned> BlockSizes;
 
@@ -41,6 +44,7 @@ namespace {
       return "PowerPC Branch Selector";
     }
   };
+  const int PPCBSel::ID = 0;
 }
 
 /// createPPCBranchSelectionPass - returns an instance of the Branch Selection
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index 6e3d68d047..acca7a30eb 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -40,8 +40,9 @@ namespace {
     int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
 
   public:
+    static const int ID;
     PPCCodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
-      : TM(T), MCE(M) {}
+      : MachineFunctionPass((intptr_t)&ID), TM(T), MCE(M) {}
 
     const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
 
@@ -63,6 +64,7 @@ namespace {
     ///
     unsigned getBinaryCodeForInstr(MachineInstr &MI);
   };
+  const int PPCCodeEmitter::ID = 0;
 }
 
 /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp
index 898b23ab50..313eab9319 100644
--- a/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -30,7 +30,9 @@ namespace {
     TargetMachine &TM;
     const TargetInstrInfo *TII;
 
-    Filler(TargetMachine &tm) : TM(tm), TII(tm.getInstrInfo()) { }
+    static const int ID;
+    Filler(TargetMachine &tm) 
+      : MachineFunctionPass((intptr_t)&ID), TM(tm), TII(tm.getInstrInfo()) { }
 
     virtual const char *getPassName() const {
       return "SPARC Delay Slot Filler";
@@ -46,6 +48,7 @@ namespace {
     }
 
   };
+  const int Filler::ID = 0;
 } // end of anonymous namespace
 
 /// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp
index f7e6506de4..5596586f0c 100644
--- a/lib/Target/Sparc/FPMover.cpp
+++ b/lib/Target/Sparc/FPMover.cpp
@@ -31,8 +31,10 @@ namespace {
     /// layout, etc.
     ///
     TargetMachine &TM;
-
-    FPMover(TargetMachine &tm) : TM(tm) { }
+    
+    static const int ID;
+    FPMover(TargetMachine &tm) 
+      : MachineFunctionPass((intptr_t)&ID), TM(tm) { }
 
     virtual const char *getPassName() const {
       return "Sparc Double-FP Move Fixer";
@@ -41,6 +43,7 @@ namespace {
     bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
     bool runOnMachineFunction(MachineFunction &F);
   };
+  const int FPMover::ID = 0;
 } // end of anonymous namespace
 
 /// createSparcFPMoverPass - Returns a pass that turns FpMOVD
diff --git a/lib/Target/TargetData.cpp b/lib/Target/TargetData.cpp
index 2cbb903b96..d1842fe7de 100644
--- a/lib/Target/TargetData.cpp
+++ b/lib/Target/TargetData.cpp
@@ -33,6 +33,7 @@ using namespace llvm;
 // Handle the Pass registration stuff necessary to use TargetData's.
 namespace {
   // Register the default SparcV9 implementation...
+  const int TargetData::ID = 0;
   RegisterPass<TargetData> X("targetdata", "Target Data Layout");
 }
 
@@ -221,7 +222,8 @@ void TargetData::init(const std::string &TargetDescription) {
   }
 }
 
-TargetData::TargetData(const Module *M) {
+TargetData::TargetData(const Module *M) 
+  : ImmutablePass((intptr_t)&ID) {
   init(M->getDataLayout());
 }
 
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index 7371aada07..db80d9f892 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -39,11 +39,14 @@ namespace {
     MachineCodeEmitter  &MCE;
     bool Is64BitMode;
   public:
+    static const int ID;
     explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
-      : II(0), TD(0), TM(tm), MCE(mce), Is64BitMode(false) {}
+      : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm), 
+      MCE(mce), Is64BitMode(false) {}
     Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
             const X86InstrInfo &ii, const TargetData &td, bool is64)
-      : II(&ii), TD(&td), TM(tm), MCE(mce), Is64BitMode(is64) {}
+      : MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm), 
+      MCE(mce), Is64BitMode(is64) {}
 
     bool runOnMachineFunction(MachineFunction &MF);
 
@@ -79,6 +82,7 @@ namespace {
     bool isX86_64ExtendedReg(const MachineOperand &MO);
     unsigned determineREX(const MachineInstr &MI);
   };
+  const int Emitter::ID = 0;
 }
 
 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 2439d19234..4667b91ba6 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -52,6 +52,9 @@ STATISTIC(NumFP  , "Number of floating point instructions");
 
 namespace {
   struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
+    static const int ID;
+    FPS() : MachineFunctionPass((intptr_t)&ID) {}
+
     virtual bool runOnMachineFunction(MachineFunction &MF);
 
     virtual const char *getPassName() const { return "X86 FP Stackifier"; }
@@ -151,6 +154,7 @@ namespace {
     void handleCondMovFP(MachineBasicBlock::iterator &I);
     void handleSpecialFP(MachineBasicBlock::iterator &I);
   };
+  const int FPS::ID = 0;
 }
 
 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }