diff options
author | Craig Topper <craig.topper@gmail.com> | 2014-04-30 07:17:30 +0000 |
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committer | Craig Topper <craig.topper@gmail.com> | 2014-04-30 07:17:30 +0000 |
commit | 7ae9b5fc7117b49605d860a735800b72ac8a9e7b (patch) | |
tree | bca21f333a0b089589364f5783882ec536349b64 /lib/Target | |
parent | ddbde80aae45be5c461efd4fa850536d185c95b8 (diff) | |
download | llvm-7ae9b5fc7117b49605d860a735800b72ac8a9e7b.tar.gz llvm-7ae9b5fc7117b49605d860a735800b72ac8a9e7b.tar.bz2 llvm-7ae9b5fc7117b49605d860a735800b72ac8a9e7b.tar.xz |
Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I introduced most of these recently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207616 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMSelectionDAGInfo.cpp | 8 | ||||
-rw-r--r-- | lib/Target/ARM64/ARM64ISelLowering.cpp | 6 | ||||
-rw-r--r-- | lib/Target/Mips/MipsSEISelLowering.cpp | 8 | ||||
-rw-r--r-- | lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 9 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 9 | ||||
-rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 2 | ||||
-rw-r--r-- | lib/Target/SystemZ/SystemZISelLowering.cpp | 4 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 9 |
8 files changed, 25 insertions, 30 deletions
diff --git a/lib/Target/ARM/ARMSelectionDAGInfo.cpp b/lib/Target/ARM/ARMSelectionDAGInfo.cpp index c18941449a..f3922035b6 100644 --- a/lib/Target/ARM/ARMSelectionDAGInfo.cpp +++ b/lib/Target/ARM/ARMSelectionDAGInfo.cpp @@ -73,7 +73,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SrcOff += VTSize; } Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, - ArrayRef<SDValue>(TFOps, i)); + makeArrayRef(TFOps, i)); for (i = 0; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { @@ -85,7 +85,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, DstOff += VTSize; } Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, - ArrayRef<SDValue>(TFOps, i)); + makeArrayRef(TFOps, i)); EmittedNumMemOps += i; } @@ -116,7 +116,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, BytesLeft -= VTSize; } Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, - ArrayRef<SDValue>(TFOps, i)); + makeArrayRef(TFOps, i)); i = 0; BytesLeft = BytesLeftSave; @@ -138,7 +138,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, BytesLeft -= VTSize; } return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, - ArrayRef<SDValue>(TFOps, i)); + makeArrayRef(TFOps, i)); } // Adjust parameters for memset, EABI uses format (ptr, size, value), diff --git a/lib/Target/ARM64/ARM64ISelLowering.cpp b/lib/Target/ARM64/ARM64ISelLowering.cpp index 502ff212be..769bcf21ed 100644 --- a/lib/Target/ARM64/ARM64ISelLowering.cpp +++ b/lib/Target/ARM64/ARM64ISelLowering.cpp @@ -4358,7 +4358,7 @@ static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask, ISD::INTRINSIC_WO_CHAIN, DL, IndexVT, DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst, DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, - ArrayRef<SDValue>(TBLMask.data(), IndexLen))); + makeArrayRef(TBLMask.data(), IndexLen))); } else { if (IndexLen == 8) { V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst); @@ -4366,7 +4366,7 @@ static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask, ISD::INTRINSIC_WO_CHAIN, DL, IndexVT, DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst, DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, - ArrayRef<SDValue>(TBLMask.data(), IndexLen))); + makeArrayRef(TBLMask.data(), IndexLen))); } else { // FIXME: We cannot, for the moment, emit a TBL2 instruction because we // cannot currently represent the register constraints on the input @@ -4378,7 +4378,7 @@ static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask, ISD::INTRINSIC_WO_CHAIN, DL, IndexVT, DAG.getConstant(Intrinsic::arm64_neon_tbl2, MVT::i32), V1Cst, V2Cst, DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, - ArrayRef<SDValue>(TBLMask.data(), IndexLen))); + makeArrayRef(TBLMask.data(), IndexLen))); } } return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle); diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index a4ff3f41eb..93a1a03a87 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -489,7 +489,7 @@ static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT, Op0->getVTList(), - ArrayRef<SDValue>(Ops, Op0->getNumOperands())); + makeArrayRef(Ops, Op0->getNumOperands())); return Op0; } } @@ -834,7 +834,7 @@ static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, Op0Op0->getOperand(2) }; DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT, Op0Op0->getVTList(), - ArrayRef<SDValue>(Ops, Op0Op0->getNumOperands())); + makeArrayRef(Ops, Op0Op0->getNumOperands())); return Op0Op0; } } @@ -1284,7 +1284,7 @@ static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB }; SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, - ArrayRef<SDValue>(Ops, ViaVecTy.getVectorNumElements())); + makeArrayRef(Ops, ViaVecTy.getVectorNumElements())); if (ViaVecTy != ResVecTy) Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result); @@ -1324,7 +1324,7 @@ static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, SplatValueA, SplatValueB, SplatValueA, SplatValueB }; SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, - ArrayRef<SDValue>(Ops, ViaVecTy.getVectorNumElements())); + makeArrayRef(Ops, ViaVecTy.getVectorNumElements())); if (VecTy != ViaVecTy) Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result); diff --git a/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp index ada4c22387..cd308806c3 100644 --- a/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp +++ b/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp @@ -1084,8 +1084,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N) { } SDValue Ops[] = { Addr, Chain }; - LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), - ArrayRef<SDValue>(Ops, 2)); + LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); } else if (Subtarget.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset) : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) { @@ -1271,8 +1270,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N) { SDValue Ops[] = { Base, Offset, Chain }; - LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), - ArrayRef<SDValue>(Ops, 3)); + LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); } else { if (Subtarget.is64Bit()) { switch (N->getOpcode()) { @@ -1455,8 +1453,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N) { } SDValue Ops[] = { Op1, Chain }; - LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), - ArrayRef<SDValue>(Ops, 2)); + LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); } MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1); diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index e787817297..e5fa0d6a24 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3474,7 +3474,7 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, // descriptor. SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue); SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, - ArrayRef<SDValue>(MTCTROps, InFlag.getNode() ? 3 : 2)); + makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2)); Chain = LoadFuncPtr.getValue(1); InFlag = LoadFuncPtr.getValue(2); @@ -3511,7 +3511,7 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, } Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, - ArrayRef<SDValue>(MTCTROps, InFlag.getNode() ? 3 : 2)); + makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2)); InFlag = Chain.getValue(1); NodeTys.clear(); @@ -3940,8 +3940,7 @@ PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee, SDValue Ops[] = { Chain, InFlag }; Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET, - dl, VTs, - ArrayRef<SDValue>(Ops, InFlag.getNode() ? 2 : 1)); + dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1)); InFlag = Chain.getValue(1); } @@ -5282,7 +5281,7 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, MVT::f64, // return register MVT::Glue // unused in this context }; - SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, ArrayRef<SDValue>()); + SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None); // Save FP register to stack slot int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index c1e12c63ca..b40cb6724d 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -1280,7 +1280,7 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const NumElements = VT.getVectorNumElements(); } Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, - ArrayRef<SDValue>(Slots, NumElements)); + makeArrayRef(Slots, NumElements)); } else { // non-constant ptr can't be folded, keeps it as a v4f32 load Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index 19da96a04b..a99647a01f 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -772,8 +772,8 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, } // Join the stores, which are independent of one another. Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, - ArrayRef<SDValue>(&MemOps[NumFixedFPRs], - SystemZ::NumArgFPRs-NumFixedFPRs)); + makeArrayRef(&MemOps[NumFixedFPRs], + SystemZ::NumArgFPRs-NumFixedFPRs)); } } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 0808eff714..0ed30f5a6f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -85,8 +85,8 @@ static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal, // If the input is a buildvector just emit a smaller one. if (Vec.getOpcode() == ISD::BUILD_VECTOR) return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT, - ArrayRef<SDUse>(Vec->op_begin()+NormalizedIdxVal, - ElemsPerChunk)); + makeArrayRef(Vec->op_begin()+NormalizedIdxVal, + ElemsPerChunk)); SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal); SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, @@ -6140,10 +6140,9 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { // Build both the lower and upper subvector. SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, - ArrayRef<SDValue>(&V[0], NumElems/2)); + makeArrayRef(&V[0], NumElems/2)); SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, - ArrayRef<SDValue>(&V[NumElems / 2], - NumElems/2)); + makeArrayRef(&V[NumElems / 2], NumElems/2)); // Recreate the wider vector with the lower and upper part. if (VT.is256BitVector()) |