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author | Bob Wilson <bob.wilson@apple.com> | 2010-09-16 04:25:37 +0000 |
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committer | Bob Wilson <bob.wilson@apple.com> | 2010-09-16 04:25:37 +0000 |
commit | 823611bfba4fb2c1abbba2e59d68432c6d0a9e9a (patch) | |
tree | eebf29767274e36e252b620212c3a30876d3c32c /lib/Target | |
parent | a8e47b3319db56675f8e80f4bb015c163110b902 (diff) | |
download | llvm-823611bfba4fb2c1abbba2e59d68432c6d0a9e9a.tar.gz llvm-823611bfba4fb2c1abbba2e59d68432c6d0a9e9a.tar.bz2 llvm-823611bfba4fb2c1abbba2e59d68432c6d0a9e9a.tar.xz |
When expanding ARM pseudo registers, copy the existing predicate operands
instead of using default predicates on the expanded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114066 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 38 |
1 files changed, 29 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 7bf4efba7b..ecf4aee3df 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -367,12 +367,21 @@ void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { if (TableEntry->HasWriteBack) MIB.addOperand(MI.getOperand(OpIdx++)); - MIB = AddDefaultPred(MIB); // For an instruction writing double-spaced subregs, the pseudo instruction - // has an extra operand that is a use of the super-register. Copy that over + // has an extra operand that is a use of the super-register. Record the + // operand index and skip over it. + unsigned SrcOpIdx = 0; + if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) + SrcOpIdx = OpIdx++; + + // Copy the predicate operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + + // Copy the super-register source operand used for double-spaced subregs over // to the new instruction as an implicit operand. - if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) { - MachineOperand MO = MI.getOperand(OpIdx); + if (SrcOpIdx != 0) { + MachineOperand MO = MI.getOperand(SrcOpIdx); MO.setImplicit(true); MIB.addOperand(MO); } @@ -407,7 +416,7 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { MIB.addOperand(MI.getOperand(OpIdx++)); bool SrcIsKill = MI.getOperand(OpIdx).isKill(); - unsigned SrcReg = MI.getOperand(OpIdx).getReg(); + unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); unsigned D0, D1, D2, D3; GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); MIB.addReg(D0).addReg(D1); @@ -415,7 +424,11 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { MIB.addReg(D2); if (NumRegs > 3) MIB.addReg(D3); - MIB = AddDefaultPred(MIB); + + // Copy the predicate operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + if (SrcIsKill) // Add an implicit kill for the super-reg. (*MIB).addRegisterKilled(SrcReg, TRI, true); @@ -491,8 +504,12 @@ void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { // Add the lane number operand. MIB.addImm(Lane); + OpIdx += 1; + + // Copy the predicate operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); - MIB = AddDefaultPred(MIB); // Copy the super-register source to be an implicit source. MO.setImplicit(true); MIB.addOperand(MO); @@ -529,9 +546,12 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, MIB.addReg(D3); // Copy the other source register operand. - MIB.addOperand(MI.getOperand(OpIdx)); + MIB.addOperand(MI.getOperand(OpIdx++)); + + // Copy the predicate operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); - MIB = AddDefaultPred(MIB); if (SrcIsKill) // Add an implicit kill for the super-reg. (*MIB).addRegisterKilled(SrcReg, TRI, true); |