Remove and simplify some more machineinstr/machineoperand stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28105 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 15 insertions, 15 deletions

diff --git a/lib/Target/X86/X86InstrBuilder.h b/lib/Target/X86/X86InstrBuilder.h
index 91a1069757..f3e1c28e4d 100644
--- a/lib/Target/X86/X86InstrBuilder.h
+++ b/lib/Target/X86/X86InstrBuilder.h
@@ -61,7 +61,7 @@ inline const MachineInstrBuilder &addDirectMem(const MachineInstrBuilder &MIB,
                                                unsigned Reg) {
   // Because memory references are always represented with four
   // values, this adds: Reg, [1, NoReg, 0] to the instruction.
-  return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(0);
+  return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0);
 }
 
 
@@ -71,14 +71,14 @@ inline const MachineInstrBuilder &addDirectMem(const MachineInstrBuilder &MIB,
 ///
 inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
                                                unsigned Reg, int Offset) {
-  return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(Offset);
+  return MIB.addReg(Reg).addImm(1).addReg(0).addImm(Offset);
 }
 
 /// addRegReg - This function is used to add a memory reference of the form:
 /// [Reg + Reg].
 inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
                                             unsigned Reg1, unsigned Reg2) {
-  return MIB.addReg(Reg1).addZImm(1).addReg(Reg2).addImm(0);
+  return MIB.addReg(Reg1).addImm(1).addReg(Reg2).addImm(0);
 }
 
 inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
@@ -91,7 +91,7 @@ inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
     MIB.addFrameIndex(AM.Base.FrameIndex);
   else
     assert (0);
-  MIB.addZImm(AM.Scale).addReg(AM.IndexReg);
+  MIB.addImm(AM.Scale).addReg(AM.IndexReg);
   if (AM.GV)
     return MIB.addGlobalAddress(AM.GV, AM.Disp);
   else
@@ -105,7 +105,7 @@ inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
 ///
 inline const MachineInstrBuilder &
 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
-  return MIB.addFrameIndex(FI).addZImm(1).addReg(0).addImm(Offset);
+  return MIB.addFrameIndex(FI).addImm(1).addReg(0).addImm(Offset);
 }
 
 /// addConstantPoolReference - This function is used to add a reference to the
@@ -117,7 +117,7 @@ addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
 inline const MachineInstrBuilder &
 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
                          int Offset = 0) {
-  return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addImm(Offset);
+  return MIB.addConstantPoolIndex(CPI).addImm(1).addReg(0).addImm(Offset);
 }
 
 } // End llvm namespace
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index e34b5112a6..a3ed62fab6 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -139,14 +139,14 @@ static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
                                  MachineInstr *MI) {
   return addFrameReference(BuildMI(Opcode, 6), FrameIndex)
       .addReg(MI->getOperand(1).getReg())
-      .addZImm(MI->getOperand(2).getImmedValue());
+      .addImm(MI->getOperand(2).getImmedValue());
 }
 
 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
                                 MachineInstr *MI) {
   if (MI->getOperand(1).isImmediate())
     return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
-      .addZImm(MI->getOperand(1).getImmedValue());
+      .addImm(MI->getOperand(1).getImmedValue());
   else if (MI->getOperand(1).isGlobalAddress())
     return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
       .addGlobalAddress(MI->getOperand(1).getGlobal(),
@@ -160,7 +160,7 @@ static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
 
 static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
                                 MachineInstr *MI) {
-  return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addZImm(0);
+  return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addImm(0);
 }
 
 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
@@ -174,7 +174,7 @@ static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
                                  MachineInstr *MI) {
   const MachineOperand& op = MI->getOperand(0);
   return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()),
-                        FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
+                        FrameIndex).addImm(MI->getOperand(2).getImmedValue());
 }
 
 
@@ -620,7 +620,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
       MachineInstr *New = 0;
       if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
         New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
-              .addZImm(Amount);
+              .addImm(Amount);
       } else {
         assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
         // factor out the amount the callee already popped.
@@ -629,7 +629,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
         if (Amount) {
           unsigned Opc = Amount < 128 ? X86::ADD32ri8 : X86::ADD32ri;
           New = BuildMI(Opc, 1, X86::ESP,
-                        MachineOperand::UseAndDef).addZImm(Amount);
+                        MachineOperand::UseAndDef).addImm(Amount);
         }
       }
 
@@ -644,7 +644,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
       unsigned Opc = CalleeAmt < 128 ? X86::SUB32ri8 : X86::SUB32ri;
       MachineInstr *New =
         BuildMI(Opc, 1, X86::ESP,
-                MachineOperand::UseAndDef).addZImm(CalleeAmt);
+                MachineOperand::UseAndDef).addImm(CalleeAmt);
       MBB.insert(I, New);
     }
   }
@@ -793,11 +793,11 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
       if (NumBytes > 0) {
         unsigned Opc = NumBytes < 128 ? X86::ADD32ri8 : X86::ADD32ri;
         BuildMI(MBB, MBBI, Opc, 2)
-          .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(NumBytes);
+          .addReg(X86::ESP, MachineOperand::UseAndDef).addImm(NumBytes);
       } else if ((int)NumBytes < 0) {
         unsigned Opc = -NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
         BuildMI(MBB, MBBI, Opc, 2)
-          .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(-NumBytes);
+          .addReg(X86::ESP, MachineOperand::UseAndDef).addImm(-NumBytes);
       }
     }
   }