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authorMatt Arsenault <Matthew.Arsenault@amd.com>2014-03-31 20:54:58 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2014-03-31 20:54:58 +0000
commit8d8c507bbfa5b2587c0b750875cd1f54f68e6b1a (patch)
tree2a0b332e55737e291eb7ea79b4858f535fee6c97 /lib/Target
parentf2529ba12735ee13f717352088ed0be2a18973d3 (diff)
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Change shouldSplitVectorElementType to better match the description.
Pass the entire vector type, and not just the element. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205247 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/NVPTX/NVPTXISelLowering.cpp4
-rw-r--r--lib/Target/NVPTX/NVPTXISelLowering.h2
-rw-r--r--lib/Target/R600/SIISelLowering.cpp4
-rw-r--r--lib/Target/R600/SIISelLowering.h2
4 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/NVPTX/NVPTXISelLowering.cpp b/lib/Target/NVPTX/NVPTXISelLowering.cpp
index e89dd17efc..8e25a657af 100644
--- a/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -331,8 +331,8 @@ const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
-bool NVPTXTargetLowering::shouldSplitVectorElementType(EVT VT) const {
- return VT == MVT::i1;
+bool NVPTXTargetLowering::shouldSplitVectorType(EVT VT) const {
+ return VT.getScalarType() == MVT::i1;
}
SDValue
diff --git a/lib/Target/NVPTX/NVPTXISelLowering.h b/lib/Target/NVPTX/NVPTXISelLowering.h
index 66e708fcea..c1e8c21958 100644
--- a/lib/Target/NVPTX/NVPTXISelLowering.h
+++ b/lib/Target/NVPTX/NVPTXISelLowering.h
@@ -141,7 +141,7 @@ public:
// PTX always uses 32-bit shift amounts
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
- virtual bool shouldSplitVectorElementType(EVT VT) const;
+ virtual bool shouldSplitVectorType(EVT VT) const override;
private:
const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
index 35bbd82af3..0b5541161f 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -211,8 +211,8 @@ bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
return VT.bitsGT(MVT::i32);
}
-bool SITargetLowering::shouldSplitVectorElementType(EVT VT) const {
- return VT.bitsLE(MVT::i16);
+bool SITargetLowering::shouldSplitVectorType(EVT VT) const {
+ return VT.getScalarType().bitsLE(MVT::i16);
}
bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h
index 9d53ba5259..ca73f53f22 100644
--- a/lib/Target/R600/SIISelLowering.h
+++ b/lib/Target/R600/SIISelLowering.h
@@ -50,7 +50,7 @@ class SITargetLowering : public AMDGPUTargetLowering {
public:
SITargetLowering(TargetMachine &tm);
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS, bool *IsFast) const;
- virtual bool shouldSplitVectorElementType(EVT VT) const;
+ virtual bool shouldSplitVectorType(EVT VT) const override;
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;