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| author | Richard Osborne <richard@xmos.com> | 2013-01-27 22:28:30 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-27 22:28:30 +0000 |
| commit | 970a479c02a418726950580e13136acd2a2dc13f (patch) | |
| tree | 21be0ccf3eb1b5b9753bfb60d01534bc776fe793 /lib/Target | |
| parent | 1cc0d5a4311c2d4bc01051561549390307b789a1 (diff) | |
| download | llvm-970a479c02a418726950580e13136acd2a2dc13f.tar.gz llvm-970a479c02a418726950580e13136acd2a2dc13f.tar.bz2 llvm-970a479c02a418726950580e13136acd2a2dc13f.tar.xz | |
[XCore] Add missing l2rus instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 9 |
2 files changed, 14 insertions, 1 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index a94f5b9c2a..c995a9c345 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -449,6 +449,12 @@ DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, case 0x12c: Inst.setOpcode(XCore::ASHR_l2rus); return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x12d: + Inst.setOpcode(XCore::OUTPW_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x12e: + Inst.setOpcode(XCore::INPW_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); case 0x13c: Inst.setOpcode(XCore::LDAWF_l2rus); return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 613f9cb278..befc096cfc 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -451,7 +451,6 @@ def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst), (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, GRRegs:$src3))]>; -// TODO inpw, outpw let mayStore=1 in { def ST16_l3r : _FL3R<0b100001100, (outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), @@ -462,6 +461,14 @@ def ST8_l3r : _FL3R<0b100011100, (outs), "st8 $val, $addr[$offset]", []>; } +def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a), + (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c", + []>; + +def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs), + (ins GRRegs:$a, GRRegs:$b, i32imm:$c), + "outpw res[$b], $a, $c", []>; + // Four operand long let Constraints = "$e = $a,$f = $b" in { def MACCU_l4r : _FL4RSrcDstSrcDst< |