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author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2014-03-02 09:19:44 +0000 |
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committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2014-03-02 09:19:44 +0000 |
commit | a9fe27ffb3aeaea3c774d16ea938b10149f348a8 (patch) | |
tree | 71f4900ffa409b619c240771d2e614569b3920dd /lib/Target | |
parent | bab807eaa132b2a909aa4d19b61fe766c73d10ee (diff) | |
download | llvm-a9fe27ffb3aeaea3c774d16ea938b10149f348a8.tar.gz llvm-a9fe27ffb3aeaea3c774d16ea938b10149f348a8.tar.bz2 llvm-a9fe27ffb3aeaea3c774d16ea938b10149f348a8.tar.xz |
AVX-512: Fixed extract_vector_elt for v8i1 vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202624 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 6 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelLowering.h | 1 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrAVX512.td | 5 | ||||
-rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 8 |
4 files changed, 14 insertions, 6 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 71aee4ff3d..3ae4147a79 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -7697,7 +7697,8 @@ static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { /// Extract one bit from mask vector, like v16i1 or v8i1. /// AVX-512 feature. -static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) { +SDValue +X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const { SDValue Vec = Op.getOperand(0); SDLoc dl(Vec); MVT VecVT = Vec.getSimpleValueType(); @@ -7717,7 +7718,8 @@ static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) { } unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); - unsigned MaxSift = VecVT.getSizeInBits() - 1; + const TargetRegisterClass* rc = getRegClassFor(VecVT); + unsigned MaxSift = rc->getSize()*8 - 1; Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec, DAG.getConstant(MaxSift - IdxVal, MVT::i8)); Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec, diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index af97b15cc1..9bf2b90f8f 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -867,6 +867,7 @@ namespace llvm { SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; + SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index 328d74f8d7..825ea09cfe 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -1213,6 +1213,11 @@ def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))), def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))), (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>; +def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))), + (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>; + +def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))), + (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>; //===----------------------------------------------------------------------===// // AVX-512 - Aligned and unaligned load and store // diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index a88b2bb1f1..33c402b69a 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -466,10 +466,10 @@ def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], // The size of the all masked registers is 16 bit because we have only one // KMOVW istruction that can store this register in memory, and it writes 2 bytes def VK1 : RegisterClass<"X86", [i1], 16, (sequence "K%u", 0, 7)>; -def VK8 : RegisterClass<"X86", [v8i1], 16, (sequence "K%u", 0, 7)>; -def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)>; +def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK1)> {let Size = 16;} +def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;} -def VK1WM : RegisterClass<"X86", [i1], 16, (sub VK1, K0)>; -def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)>; +def VK1WM : RegisterClass<"X86", [i1], 16, (sub VK1, K0)> {let Size = 16;} +def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;} def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>; |