diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-04-22 20:13:37 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-04-22 20:13:37 +0000 |
| commit | b109ea8245e2948ea6d06a6e6cbab7c6788da211 (patch) | |
| tree | bd0c7dcdcb9142de21c1fc66aa3cfa7faaaef736 /lib/Target | |
| parent | d597263b9442923bacc24f26a8510fb69f992864 (diff) | |
| download | llvm-b109ea8245e2948ea6d06a6e6cbab7c6788da211.tar.gz llvm-b109ea8245e2948ea6d06a6e6cbab7c6788da211.tar.bz2 llvm-b109ea8245e2948ea6d06a6e6cbab7c6788da211.tar.xz | |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180040 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/Mips/Mips16ISelLowering.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsOs16.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSEISelLowering.cpp | 7 |
3 files changed, 9 insertions, 6 deletions
diff --git a/lib/Target/Mips/Mips16ISelLowering.cpp b/lib/Target/Mips/Mips16ISelLowering.cpp index 16f0626fcd..f63318f1e6 100644 --- a/lib/Target/Mips/Mips16ISelLowering.cpp +++ b/lib/Target/Mips/Mips16ISelLowering.cpp @@ -613,7 +613,8 @@ MachineBasicBlock unsigned regX = MI->getOperand(0).getReg(); unsigned regY = MI->getOperand(1).getReg(); MachineBasicBlock *target = MI->getOperand(2).getMBB(); - BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY); + BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) + .addReg(regY); BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); MI->eraseFromParent(); // The pseudo instruction is gone now. return BB; @@ -635,7 +636,8 @@ MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins( CmpOpc = CmpiXOpc; else llvm_unreachable("immediate field not usable"); - BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm); + BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) + .addImm(imm); BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); MI->eraseFromParent(); // The pseudo instruction is gone now. return BB; diff --git a/lib/Target/Mips/MipsOs16.cpp b/lib/Target/Mips/MipsOs16.cpp index aabc466369..1919077eeb 100644 --- a/lib/Target/Mips/MipsOs16.cpp +++ b/lib/Target/Mips/MipsOs16.cpp @@ -1,4 +1,4 @@ -//===---- MipsOs16.cpp for Mips Option -Os16 --------===// +//===---- MipsOs16.cpp for Mips Option -Os16 --------===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index 23d2578b07..7ba3123711 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -131,7 +131,8 @@ SDValue MipsSETargetLowering::LowerOperation(SDValue Op, case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); - case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG); + case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, + DAG); case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG); case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG); } @@ -328,8 +329,8 @@ static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); if (!BV || - !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, EltSize, - !Subtarget->isLittle()) || + !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, + EltSize,!Subtarget->isLittle()) || (SplatBitSize != EltSize) || !isUIntN(Log2_32(EltSize), SplatValue.getZExtValue())) return SDValue(); |