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authorAkira Hatanaka <ahatanaka@mips.com>2013-04-13 00:45:02 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2013-04-13 00:45:02 +0000
commitbf308cedce5caca4c73e558611a1c8c48687d62e (patch)
treed2785848c440b5747f8ce3fe43cd971986739b7e /lib/Target
parent41a10b6c4ecb0bdd17466bd569eaf4b8f103e240 (diff)
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[mips] Override TargetLoweringBase::isShuffleMaskLegal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179433 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/Mips/MipsSEISelLowering.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsSEISelLowering.h b/lib/Target/Mips/MipsSEISelLowering.h
index 186f6a343d..90e83330a7 100644
--- a/lib/Target/Mips/MipsSEISelLowering.h
+++ b/lib/Target/Mips/MipsSEISelLowering.h
@@ -31,6 +31,11 @@ namespace llvm {
virtual MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
+ virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
+ EVT VT) const {
+ return false;
+ }
+
virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
if (VT == MVT::Untyped)
return Subtarget->hasDSP() ? &Mips::ACRegsDSPRegClass :