diff options
author | Torok Edwin <edwintorok@gmail.com> | 2009-07-14 16:55:14 +0000 |
---|---|---|
committer | Torok Edwin <edwintorok@gmail.com> | 2009-07-14 16:55:14 +0000 |
commit | c23197a26f34f559ea9797de51e187087c039c42 (patch) | |
tree | bf497ec9a02cd2fc0b64e3e58eff037a719a854d /lib/Target | |
parent | 1f316e321a8f2fa0e193c5444584a67a8aabe9a8 (diff) | |
download | llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.gz llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.bz2 llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.xz |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
81 files changed, 396 insertions, 396 deletions
diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h index 471c212583..3c0cfa5121 100644 --- a/lib/Target/ARM/ARM.h +++ b/lib/Target/ARM/ARM.h @@ -52,7 +52,7 @@ namespace ARMCC { inline static CondCodes getOppositeCondition(CondCodes CC){ switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code"); + default: llvm_unreachable("Unknown condition code"); case EQ: return NE; case NE: return EQ; case HS: return LO; @@ -73,7 +73,7 @@ namespace ARMCC { inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code"); + default: llvm_unreachable("Unknown condition code"); case ARMCC::EQ: return "eq"; case ARMCC::NE: return "ne"; case ARMCC::HS: return "hs"; diff --git a/lib/Target/ARM/ARMAddressingModes.h b/lib/Target/ARM/ARMAddressingModes.h index 40e3e8690f..5bbf35d296 100644 --- a/lib/Target/ARM/ARMAddressingModes.h +++ b/lib/Target/ARM/ARMAddressingModes.h @@ -38,7 +38,7 @@ namespace ARM_AM { static inline const char *getShiftOpcStr(ShiftOpc Op) { switch (Op) { - default: LLVM_UNREACHABLE("Unknown shift opc!"); + default: llvm_unreachable("Unknown shift opc!"); case ARM_AM::asr: return "asr"; case ARM_AM::lsl: return "lsl"; case ARM_AM::lsr: return "lsr"; @@ -71,7 +71,7 @@ namespace ARM_AM { static inline const char *getAMSubModeStr(AMSubMode Mode) { switch (Mode) { - default: LLVM_UNREACHABLE("Unknown addressing sub-mode!"); + default: llvm_unreachable("Unknown addressing sub-mode!"); case ARM_AM::ia: return "ia"; case ARM_AM::ib: return "ib"; case ARM_AM::da: return "da"; @@ -81,7 +81,7 @@ namespace ARM_AM { static inline const char *getAMSubModeAltStr(AMSubMode Mode, bool isLD) { switch (Mode) { - default: LLVM_UNREACHABLE("Unknown addressing sub-mode!"); + default: llvm_unreachable("Unknown addressing sub-mode!"); case ARM_AM::ia: return isLD ? "fd" : "ea"; case ARM_AM::ib: return isLD ? "ed" : "fa"; case ARM_AM::da: return isLD ? "fa" : "ed"; diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 9bca6a787d..a8a519a5ec 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -434,7 +434,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { return 0; switch (MI->getOpcode()) { default: - LLVM_UNREACHABLE("Unknown or unset size field for instr!"); + llvm_unreachable("Unknown or unset size field for instr!"); case TargetInstrInfo::IMPLICIT_DEF: case TargetInstrInfo::DECLARE: case TargetInstrInfo::DBG_LABEL: diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 41b061a123..53ce753412 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -72,7 +72,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum) { case S30: return 30; case S31: return 31; default: - LLVM_UNREACHABLE("Unknown ARM register!"); + llvm_unreachable("Unknown ARM register!"); } } @@ -83,7 +83,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, using namespace ARM; switch (RegEnum) { default: - LLVM_UNREACHABLE("Unknown ARM register!"); + llvm_unreachable("Unknown ARM register!"); case R0: case D0: return 0; case R1: case D1: return 1; case R2: case D2: return 2; @@ -707,12 +707,12 @@ unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const { } unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } @@ -1138,7 +1138,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, break; } default: - LLVM_UNREACHABLE("Unsupported addressing mode!"); + llvm_unreachable("Unsupported addressing mode!"); break; } diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 696547d556..3442fcd4f9 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -223,7 +223,7 @@ bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) { template<class CodeEmitter> unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const { switch (ARM_AM::getAM2ShiftOpc(Imm)) { - default: LLVM_UNREACHABLE("Unknown shift opc!"); + default: llvm_unreachable("Unknown shift opc!"); case ARM_AM::asr: return 2; case ARM_AM::lsl: return 0; case ARM_AM::lsr: return 1; @@ -260,7 +260,7 @@ unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI, #ifndef NDEBUG cerr << MO; #endif - llvm_unreachable(); + llvm_unreachable(0); } return 0; } @@ -340,7 +340,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) { NumEmitted++; // Keep track of the # of mi's emitted switch (MI.getDesc().TSFlags & ARMII::FormMask) { default: { - LLVM_UNREACHABLE("Unhandled instruction encoding format!"); + llvm_unreachable("Unhandled instruction encoding format!"); break; } case ARMII::Pseudo: @@ -458,10 +458,10 @@ void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) { else if (CFP->getType() == Type::DoubleTy) emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); else { - LLVM_UNREACHABLE("Unable to handle this constantpool entry!"); + llvm_unreachable("Unable to handle this constantpool entry!"); } } else { - LLVM_UNREACHABLE("Unable to handle this constantpool entry!"); + llvm_unreachable("Unable to handle this constantpool entry!"); } } } @@ -589,7 +589,7 @@ void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) { unsigned Opcode = MI.getDesc().Opcode; switch (Opcode) { default: - LLVM_UNREACHABLE("ARMCodeEmitter::emitPseudoInstruction");//FIXME: + llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");//FIXME: case TargetInstrInfo::INLINEASM: { // We allow inline assembler nodes with empty bodies - they can // implicitly define registers, which is ok for JIT. @@ -676,7 +676,7 @@ unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue( // ROR - 0111 // RRX - 0110 and bit[11:8] clear. switch (SOpc) { - default: LLVM_UNREACHABLE("Unknown shift opc!"); + default: llvm_unreachable("Unknown shift opc!"); case ARM_AM::lsl: SBits = 0x1; break; case ARM_AM::lsr: SBits = 0x3; break; case ARM_AM::asr: SBits = 0x5; break; @@ -690,7 +690,7 @@ unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue( // ASR - 100 // ROR - 110 switch (SOpc) { - default: LLVM_UNREACHABLE("Unknown shift opc!"); + default: llvm_unreachable("Unknown shift opc!"); case ARM_AM::lsl: SBits = 0x0; break; case ARM_AM::lsr: SBits = 0x2; break; case ARM_AM::asr: SBits = 0x4; break; @@ -959,7 +959,7 @@ static unsigned getAddrModeUPBits(unsigned Mode) { // DA - Decrement after - bit U = 0 and bit P = 0 // DB - Decrement before - bit U = 0 and bit P = 1 switch (Mode) { - default: LLVM_UNREACHABLE("Unknown addressing sub-mode!"); + default: llvm_unreachable("Unknown addressing sub-mode!"); case ARM_AM::da: break; case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; @@ -1123,7 +1123,7 @@ void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); if (TID.Opcode == ARM::TPsoft) { - LLVM_UNREACHABLE("ARM::TPsoft FIXME"); // FIXME + llvm_unreachable("ARM::TPsoft FIXME"); // FIXME } // Part of binary is determined by TableGn. diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp index 1f2376e638..0a160b6d12 100644 --- a/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -449,7 +449,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn, Bits = 8; // Taking the address of a CP entry. break; } - LLVM_UNREACHABLE("Unknown addressing mode for CP reference!"); + llvm_unreachable("Unknown addressing mode for CP reference!"); case ARMII::AddrMode1: // AM1: 8 bits << 2 Bits = 8; Scale = 4; // Taking the address of a CP entry. diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 83aa60f303..9420d21273 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -470,7 +470,7 @@ unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const { /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code!"); + default: llvm_unreachable("Unknown condition code!"); case ISD::SETNE: return ARMCC::NE; case ISD::SETEQ: return ARMCC::EQ; case ISD::SETGT: return ARMCC::GT; @@ -492,7 +492,7 @@ static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool Invert = false; CondCode2 = ARMCC::AL; switch (CC) { - default: LLVM_UNREACHABLE("Unknown FP condition!"); + default: llvm_unreachable("Unknown FP condition!"); case ISD::SETEQ: case ISD::SETOEQ: CondCode = ARMCC::EQ; break; case ISD::SETGT: @@ -661,7 +661,7 @@ CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC, bool Return) const { switch (CC) { default: - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); case CallingConv::C: case CallingConv::Fast: // Use target triple & subtarget features to do actual dispatch. @@ -745,7 +745,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, } switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::BCvt: Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val); @@ -858,7 +858,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); @@ -1060,7 +1060,7 @@ SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { SDValue Arg = Op.getOperand(realRVLocIdx*2+1); switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::BCvt: Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); @@ -1442,7 +1442,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { // to 32 bits. Insert an assert[sz]ext to capture this, then // truncate to the right size. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::BCvt: ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); @@ -2006,7 +2006,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { if (Op.getOperand(1).getValueType().isFloatingPoint()) { switch (SetCCOpcode) { - default: LLVM_UNREACHABLE("Illegal FP comparison"); break; + default: llvm_unreachable("Illegal FP comparison"); break; case ISD::SETUNE: case ISD::SETNE: Invert = true; // Fallthrough case ISD::SETOEQ: @@ -2045,7 +2045,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { } else { // Integer comparisons. switch (SetCCOpcode) { - default: LLVM_UNREACHABLE("Illegal integer comparison"); break; + default: llvm_unreachable("Illegal integer comparison"); break; case ISD::SETNE: Invert = true; case ISD::SETEQ: Opc = ARMISD::VCEQ; break; case ISD::SETLT: Swap = true; @@ -2149,7 +2149,7 @@ static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef, } default: - LLVM_UNREACHABLE("unexpected size for isVMOVSplat"); + llvm_unreachable("unexpected size for isVMOVSplat"); break; } @@ -2191,7 +2191,7 @@ static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) { case 16: CanonicalVT = MVT::v4i16; break; case 32: CanonicalVT = MVT::v2i32; break; case 64: CanonicalVT = MVT::v1i64; break; - default: LLVM_UNREACHABLE("unexpected splat element type"); break; + default: llvm_unreachable("unexpected splat element type"); break; } } else { assert(VT.is128BitVector() && "unknown splat vector size"); @@ -2200,7 +2200,7 @@ static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) { case 16: CanonicalVT = MVT::v8i16; break; case 32: CanonicalVT = MVT::v4i32; break; case 64: CanonicalVT = MVT::v2i64; break; - default: LLVM_UNREACHABLE("unexpected splat element type"); break; + default: llvm_unreachable("unexpected splat element type"); break; } } @@ -2260,7 +2260,7 @@ static SDValue LowerCONCAT_VECTORS(SDValue Op) { SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Don't know how to custom lower this!"); + default: llvm_unreachable("Don't know how to custom lower this!"); case ISD::ConstantPool: return LowerConstantPool(Op, DAG); case ISD::GlobalAddress: return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : @@ -2303,7 +2303,7 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { switch (N->getOpcode()) { default: - LLVM_UNREACHABLE("Don't know how to custom expand this!"); + llvm_unreachable("Don't know how to custom expand this!"); return; case ISD::BIT_CONVERT: Results.push_back(ExpandBIT_CONVERT(N, DAG)); @@ -2595,7 +2595,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { case Intrinsic::arm_neon_vshiftlu: if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) break; - LLVM_UNREACHABLE("invalid shift count for vshll intrinsic"); + llvm_unreachable("invalid shift count for vshll intrinsic"); case Intrinsic::arm_neon_vrshifts: case Intrinsic::arm_neon_vrshiftu: @@ -2612,7 +2612,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { case Intrinsic::arm_neon_vqshiftsu: if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) break; - LLVM_UNREACHABLE("invalid shift count for vqshlu intrinsic"); + llvm_unreachable("invalid shift count for vqshlu intrinsic"); case Intrinsic::arm_neon_vshiftn: case Intrinsic::arm_neon_vrshiftn: @@ -2625,10 +2625,10 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { // Narrowing shifts require an immediate right shift. if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) break; - LLVM_UNREACHABLE("invalid shift count for narrowing vector shift intrinsic"); + llvm_unreachable("invalid shift count for narrowing vector shift intrinsic"); default: - LLVM_UNREACHABLE("unhandled vector shift"); + llvm_unreachable("unhandled vector shift"); } switch (IntNo) { @@ -2686,7 +2686,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) VShiftOpc = ARMISD::VSRI; else { - LLVM_UNREACHABLE("invalid shift count for vsli/vsri intrinsic"); + llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); } return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), @@ -2720,7 +2720,7 @@ static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, int64_t Cnt; switch (N->getOpcode()) { - default: LLVM_UNREACHABLE("unexpected shift opcode"); + default: llvm_unreachable("unexpected shift opcode"); case ISD::SHL: if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) @@ -2763,7 +2763,7 @@ static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, unsigned Opc = 0; switch (N->getOpcode()) { - default: LLVM_UNREACHABLE("unexpected opcode"); + default: llvm_unreachable("unexpected opcode"); case ISD::SIGN_EXTEND: Opc = ARMISD::VGETLANEs; break; diff --git a/lib/Target/ARM/ARMJITInfo.cpp b/lib/Target/ARM/ARMJITInfo.cpp index a030a8c422..f67bd8cc59 100644 --- a/lib/Target/ARM/ARMJITInfo.cpp +++ b/lib/Target/ARM/ARMJITInfo.cpp @@ -104,7 +104,7 @@ extern "C" { ); #else // Not an ARM host void ARMCompilationCallback() { - LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!"); + llvm_unreachable("Cannot call ARMCompilationCallback() on a non-ARM arch!"); } #endif } @@ -123,12 +123,12 @@ extern "C" void ARMCompilationCallbackC(intptr_t StubAddr) { // ldr pc, [pc,#-4] // <addr> if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) { - LLVM_UNREACHABLE("ERROR: Unable to mark stub writable"); + llvm_unreachable("ERROR: Unable to mark stub writable"); } *(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4] *(intptr_t *)(StubAddr+4) = NewVal; if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) { - LLVM_UNREACHABLE("ERROR: Unable to mark stub executable"); + llvm_unreachable("ERROR: Unable to mark stub executable"); } } diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 1d62707527..13bed950d1 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -138,7 +138,7 @@ static int getLoadStoreMultipleOpcode(int Opcode) { case ARM::FSTD: NumFSTMGened++; return ARM::FSTMD; - default: LLVM_UNREACHABLE("Unhandled opcode!"); + default: llvm_unreachable("Unhandled opcode!"); } return 0; } @@ -513,7 +513,7 @@ static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) { case ARM::t2STRi8: case ARM::t2STRi12: return ARM::t2STR_PRE; - default: LLVM_UNREACHABLE("Unhandled opcode!"); + default: llvm_unreachable("Unhandled opcode!"); } return 0; } @@ -532,7 +532,7 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) { case ARM::t2STRi8: case ARM::t2STRi12: return ARM::t2STR_POST; - default: LLVM_UNREACHABLE("Unhandled opcode!"); + default: llvm_unreachable("Unhandled opcode!"); } return 0; } diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp index 0a55c0c397..f878a768f6 100644 --- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp @@ -211,7 +211,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { // Print out labels for the function. const Function *F = MF.getFunction(); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::PrivateLinkage: case Function::InternalLinkage: SwitchToTextSection("\t.text", F); @@ -308,7 +308,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, O << TRI->getAsmName(Reg); } } else - LLVM_UNREACHABLE("not implemented"); + llvm_unreachable("not implemented"); break; } case MachineOperand::MO_Immediate: { @@ -1139,7 +1139,7 @@ void ARMAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::InternalLinkage: break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 940eea4d5b..9c544e337a 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -511,7 +511,7 @@ void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, break; } default: - LLVM_UNREACHABLE("Unsupported addressing mode!"); + llvm_unreachable("Unsupported addressing mode!"); break; } diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp index 9a7c5a4f86..98eeb8983e 100644 --- a/lib/Target/Alpha/AlphaCodeEmitter.cpp +++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp @@ -166,7 +166,7 @@ static unsigned getAlphaRegNumber(unsigned Reg) { case Alpha::R30 : case Alpha::F30 : return 30; case Alpha::R31 : case Alpha::F31 : return 31; default: - LLVM_UNREACHABLE("Unhandled reg"); + llvm_unreachable("Unhandled reg"); } } @@ -217,7 +217,7 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, Offset = MI.getOperand(3).getImm(); break; default: - LLVM_UNREACHABLE("unknown relocatable instruction"); + llvm_unreachable("unknown relocatable instruction"); } if (MO.isGlobal()) MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), @@ -238,7 +238,7 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, #ifndef NDEBUG cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } return rv; diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 977e621b65..0f4d0f42ca 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -338,7 +338,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { bool rev = false; bool inv = false; switch(CC) { - default: DEBUG(N->dump(CurDAG)); LLVM_UNREACHABLE("Unknown FP comparison!"); + default: DEBUG(N->dump(CurDAG)); llvm_unreachable("Unknown FP comparison!"); case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: Opc = Alpha::CMPTEQ; break; case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: @@ -472,7 +472,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { } else if (TypeOperands[i] == MVT::f64) { Opc = Alpha::STT; } else - LLVM_UNREACHABLE("Unknown operand"); + llvm_unreachable("Unknown operand"); SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8), CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64), @@ -489,7 +489,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { CallOperands[i], InFlag); InFlag = Chain.getValue(1); } else - LLVM_UNREACHABLE("Unknown operand"); + llvm_unreachable("Unknown operand"); } // Finally, once everything is in registers to pass to the call, emit the @@ -512,7 +512,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { std::vector<SDValue> CallResults; switch (N->getValueType(0).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ret value!"); + default: llvm_unreachable("Unexpected ret value!"); case MVT::Other: break; case MVT::i64: Chain = CurDAG->getCopyFromReg(Chain, dl, diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 289353631e..9097a8a9de 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -314,7 +314,7 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { SDValue()); switch (Op.getNumOperands()) { default: - LLVM_UNREACHABLE("Do not know how to return this many arguments!"); + llvm_unreachable("Do not know how to return this many arguments!"); case 1: break; //return SDValue(); // ret void is legal @@ -380,7 +380,7 @@ AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, for (unsigned i = 0, e = Args.size(); i != e; ++i) { switch (getValueType(Args[i].Ty).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ValueType for argument!"); + default: llvm_unreachable("Unexpected ValueType for argument!"); case MVT::i1: case MVT::i8: case MVT::i16: @@ -476,7 +476,7 @@ void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain, SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Wasn't expecting to be able to lower this!"); + default: llvm_unreachable("Wasn't expecting to be able to lower this!"); case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsBase, VarArgsOffset); @@ -527,7 +527,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { return Lo; } case ISD::GlobalTLSAddress: - LLVM_UNREACHABLE("TLS not implemented for Alpha."); + llvm_unreachable("TLS not implemented for Alpha."); case ISD::GlobalAddress: { GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalValue *GV = GSDN->getGlobal(); diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 139a4db655..3cb2ce3720 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -201,7 +201,7 @@ AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); } void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -217,7 +217,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else if (RC == Alpha::GPRCRegisterClass) Opc = Alpha::STQ; else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)); @@ -246,7 +246,7 @@ AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); } void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, @@ -261,7 +261,7 @@ void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, else if (RC == Alpha::GPRCRegisterClass) Opc = Alpha::LDQ; else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); @@ -332,7 +332,7 @@ static unsigned AlphaRevCondCode(unsigned Opcode) { case Alpha::FBLE: return Alpha::FBGT; case Alpha::FBLT: return Alpha::FBGE; default: - LLVM_UNREACHABLE("Unknown opcode"); + llvm_unreachable("Unknown opcode"); } return 0; // Not reached } diff --git a/lib/Target/Alpha/AlphaJITInfo.cpp b/lib/Target/Alpha/AlphaJITInfo.cpp index 8919dc0492..4feb2776ec 100644 --- a/lib/Target/Alpha/AlphaJITInfo.cpp +++ b/lib/Target/Alpha/AlphaJITInfo.cpp @@ -72,7 +72,7 @@ static void EmitBranchToAt(void *At, void *To) { void AlphaJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { //FIXME - llvm_unreachable(); + llvm_unreachable(0); } static TargetJITInfo::JITCompilerFn JITCompilerFunction; @@ -185,7 +185,7 @@ extern "C" { ); #else void AlphaCompilationCallback() { - LLVM_UNREACHABLE("Cannot call AlphaCompilationCallback() on a non-Alpha arch!"); + llvm_unreachable("Cannot call AlphaCompilationCallback() on a non-Alpha arch!"); } #endif } @@ -241,7 +241,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR, long idx = 0; bool doCommon = true; switch ((Alpha::RelocationType)MR->getRelocationType()) { - default: LLVM_UNREACHABLE("Unknown relocation type!"); + default: llvm_unreachable("Unknown relocation type!"); case Alpha::reloc_literal: //This is a LDQl idx = MR->getGOTIndex(); @@ -281,7 +281,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR, DOUT << "LDA: " << idx << "\n"; break; default: - LLVM_UNREACHABLE("Cannot handle gpdist yet"); + llvm_unreachable("Cannot handle gpdist yet"); } break; case Alpha::reloc_bsr: { diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index f1e651c6a8..0c4a36a61b 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -307,7 +307,7 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, } unsigned AlphaRegisterInfo::getRARegister() const { - LLVM_UNREACHABLE("What is the return address register"); + llvm_unreachable("What is the return address register"); return 0; } @@ -316,17 +316,17 @@ unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const { } unsigned AlphaRegisterInfo::getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned AlphaRegisterInfo::getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("What is the dwarf register number"); + llvm_unreachable("What is the dwarf register number"); return -1; } diff --git a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp index 38bdeb25c0..1e3e83c841 100644 --- a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp +++ b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp @@ -101,7 +101,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { return; case MachineOperand::MO_Immediate: - LLVM_UNREACHABLE("printOp() does not handle immediate values"); + llvm_unreachable("printOp() does not handle immediate values"); return; case MachineOperand::MO_MachineBasicBlock: @@ -155,7 +155,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) { EmitAlignment(MF.getAlignment(), F); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::InternalLinkage: // Symbols default to internal. case Function::PrivateLinkage: break; @@ -188,7 +188,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) { // Print the assembly for the instruction. ++EmittedInsts; if (!printInstruction(II)) { - LLVM_UNREACHABLE("Unhandled instruction in asm writer!"); + llvm_unreachable("Unhandled instruction in asm writer!"); } } } @@ -248,7 +248,7 @@ void AlphaAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::PrivateLinkage: break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } // 3: Type, Size, Align diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp index c3c2b0ed43..09ff9a2d4b 100644 --- a/lib/Target/CBackend/CBackend.cpp +++ b/lib/Target/CBackend/CBackend.cpp @@ -289,11 +289,11 @@ namespace { void visitBranchInst(BranchInst &I); void visitSwitchInst(SwitchInst &I); void visitInvokeInst(InvokeInst &I) { - LLVM_UNREACHABLE("Lowerinvoke pass didn't work!"); + llvm_unreachable("Lowerinvoke pass didn't work!"); } void visitUnwindInst(UnwindInst &I) { - LLVM_UNREACHABLE("Lowerinvoke pass didn't work!"); + llvm_unreachable("Lowerinvoke pass didn't work!"); } void visitUnreachableInst(UnreachableInst &I); @@ -327,7 +327,7 @@ namespace { #ifndef NDEBUG cerr << "C Writer does not know about " << I; #endif - llvm_unreachable(); + llvm_unreachable(0); } void outputLValue(Instruction *I) { @@ -513,7 +513,7 @@ CWriter::printSimpleType(raw_ostream &Out, const Type *Ty, bool isSigned, #ifndef NDEBUG cerr << "Unknown primitive type: " << *Ty << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } @@ -560,7 +560,7 @@ CWriter::printSimpleType(std::ostream &Out, const Type *Ty, bool isSigned, #ifndef NDEBUG cerr << "Unknown primitive type: " << *Ty << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } @@ -661,7 +661,7 @@ raw_ostream &CWriter::printType(raw_ostream &Out, const Type *Ty, return Out << TyName << ' ' << NameSoFar; } default: - LLVM_UNREACHABLE("Unhandled case in getTypeProps!"); + llvm_unreachable("Unhandled case in getTypeProps!"); } return Out; @@ -764,7 +764,7 @@ std::ostream &CWriter::printType(std::ostream &Out, const Type *Ty, return Out << TyName << ' ' << NameSoFar; } default: - LLVM_UNREACHABLE("Unhandled case in getTypeProps!"); + llvm_unreachable("Unhandled case in getTypeProps!"); } return Out; @@ -923,7 +923,7 @@ void CWriter::printCast(unsigned opc, const Type *SrcTy, const Type *DstTy) { Out << ')'; break; default: - LLVM_UNREACHABLE("Invalid cast opcode"); + llvm_unreachable("Invalid cast opcode"); } // Print the source type cast @@ -953,7 +953,7 @@ void CWriter::printCast(unsigned opc, const Type *SrcTy, const Type *DstTy) { case Instruction::FPToUI: break; // These don't need a source cast. default: - LLVM_UNREACHABLE("Invalid cast opcode"); + llvm_unreachable("Invalid cast opcode"); break; } } @@ -1062,10 +1062,10 @@ void CWriter::printConstant(Constant *CPV, bool Static) { case ICmpInst::ICMP_UGT: Out << " > "; break; case ICmpInst::ICMP_SGE: case ICmpInst::ICMP_UGE: Out << " >= "; break; - default: LLVM_UNREACHABLE("Illegal ICmp predicate"); + default: llvm_unreachable("Illegal ICmp predicate"); } break; - default: LLVM_UNREACHABLE("Illegal opcode here!"); + default: llvm_unreachable("Illegal opcode here!"); } printConstantWithCast(CE->getOperand(1), CE->getOpcode()); if (NeedsClosingParens) @@ -1083,7 +1083,7 @@ void CWriter::printConstant(Constant *CPV, bool Static) { else { const char* op = 0; switch (CE->getPredicate()) { - default: LLVM_UNREACHABLE("Illegal FCmp predicate"); + default: llvm_unreachable("Illegal FCmp predicate"); case FCmpInst::FCMP_ORD: op = "ord"; break; case FCmpInst::FCMP_UNO: op = "uno"; break; case FCmpInst::FCMP_UEQ: op = "ueq"; break; @@ -1115,7 +1115,7 @@ void CWriter::printConstant(Constant *CPV, bool Static) { cerr << "CWriter Error: Unhandled constant expression: " << *CE << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } else if (isa<UndefValue>(CPV) && CPV->getType()->isSingleValueType()) { Out << "(("; @@ -1324,7 +1324,7 @@ void CWriter::printConstant(Constant *CPV, bool Static) { #ifndef NDEBUG cerr << "Unknown constant type: " << *CPV << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } @@ -2128,7 +2128,7 @@ void CWriter::printFloatingPointConstants(const Constant *C) { << "}; /* Long double constant */\n"; } else { - LLVM_UNREACHABLE("Unknown float type!"); + llvm_unreachable("Unknown float type!"); } } @@ -2680,7 +2680,7 @@ void CWriter::visitBinaryOperator(Instruction &I) { #ifndef NDEBUG cerr << "Invalid operator type!" << I; #endif - llvm_unreachable(); + llvm_unreachable(0); } writeOperandWithCast(I.getOperand(1), I.getOpcode()); @@ -2721,7 +2721,7 @@ void CWriter::visitICmpInst(ICmpInst &I) { #ifndef NDEBUG cerr << "Invalid icmp predicate!" << I; #endif - llvm_unreachable(); + llvm_unreachable(0); } writeOperandWithCast(I.getOperand(1), I); @@ -2745,7 +2745,7 @@ void CWriter::visitFCmpInst(FCmpInst &I) { const char* op = 0; switch (I.getPredicate()) { - default: LLVM_UNREACHABLE("Illegal FCmp predicate"); + default: llvm_unreachable("Illegal FCmp predicate"); case FCmpInst::FCMP_ORD: op = "ord"; break; case FCmpInst::FCMP_UNO: op = "uno"; break; case FCmpInst::FCMP_UEQ: op = "ueq"; break; @@ -2773,7 +2773,7 @@ void CWriter::visitFCmpInst(FCmpInst &I) { static const char * getFloatBitCastField(const Type *Ty) { switch (Ty->getTypeID()) { - default: LLVM_UNREACHABLE("Invalid Type"); + default: llvm_unreachable("Invalid Type"); case Type::FloatTyID: return "Float"; case Type::DoubleTyID: return "Double"; case Type::IntegerTyID: { @@ -3136,7 +3136,7 @@ bool CWriter::visitBuiltinCall(CallInst &I, Intrinsic::ID ID, Out << ')'; // Multiple GCC builtins multiplex onto this intrinsic. switch (cast<ConstantInt>(I.getOperand(3))->getZExtValue()) { - default: LLVM_UNREACHABLE("Invalid llvm.x86.sse.cmp!"); + default: llvm_unreachable("Invalid llvm.x86.sse.cmp!"); case 0: Out << "__builtin_ia32_cmpeq"; break; case 1: Out << "__builtin_ia32_cmplt"; break; case 2: Out << "__builtin_ia32_cmple"; break; @@ -3348,7 +3348,7 @@ void CWriter::visitInlineAsm(CallInst &CI) { } void CWriter::visitMallocInst(MallocInst &I) { - LLVM_UNREACHABLE("lowerallocations pass didn't work!"); + llvm_unreachable("lowerallocations pass didn't work!"); } void CWriter::visitAllocaInst(AllocaInst &I) { @@ -3365,7 +3365,7 @@ void CWriter::visitAllocaInst(AllocaInst &I) { } void CWriter::visitFreeInst(FreeInst &I) { - LLVM_UNREACHABLE("lowerallocations pass didn't work!"); + llvm_unreachable("lowerallocations pass didn't work!"); } void CWriter::printGEPExpression(Value *Ptr, gep_type_iterator I, diff --git a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp index 77e66c80e7..bc4facda9f 100644 --- a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp +++ b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp @@ -265,7 +265,7 @@ namespace { && "Invalid negated immediate rotate 7-bit argument"); O << -value; } else { - LLVM_UNREACHABLE("Invalid/non-immediate rotate amount in printRotateNeg7Imm"); + llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm"); } } @@ -276,7 +276,7 @@ namespace { && "Invalid negated immediate rotate 7-bit argument"); O << -value; } else { - LLVM_UNREACHABLE("Invalid/non-immediate rotate amount in printRotateNeg7Imm"); + llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm"); } } @@ -434,7 +434,7 @@ LinuxAsmPrinter::runOnMachineFunction(MachineFunction &MF) EmitAlignment(MF.getAlignment(), F); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::PrivateLinkage: case Function::InternalLinkage: // Symbols default to internal. break; diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index ddb9a36885..8f704ecaa5 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -378,7 +378,7 @@ namespace { break; case 'v': // not offsetable #if 1 - LLVM_UNREACHABLE("InlineAsmMemoryOperand 'v' constraint not handled."); + llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled."); #else SelectAddrIdxOnly(Op, Op, Op0, Op1); #endif diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 6b9df67d6c..2042a93e91 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -875,7 +875,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { } } - LLVM_UNREACHABLE("LowerConstantPool: Relocation model other than static" + llvm_unreachable("LowerConstantPool: Relocation model other than static" " not supported."); return SDValue(); } @@ -906,7 +906,7 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { } } - LLVM_UNREACHABLE("LowerJumpTable: Relocation model other than static" + llvm_unreachable("LowerJumpTable: Relocation model other than static" " not supported."); return SDValue(); } @@ -1138,7 +1138,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); switch (Arg.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ValueType for argument!"); + default: llvm_unreachable("Unexpected ValueType for argument!"); case MVT::i8: case MVT::i16: case MVT::i32: @@ -1270,7 +1270,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // If the call has results, copy the values out of the ret val registers. switch (TheCall->getValueType(0).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ret value!"); + default: llvm_unreachable("Unexpected ret value!"); case MVT::Other: break; case MVT::i32: if (TheCall->getValueType(1) == MVT::i32) { @@ -1738,7 +1738,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { } else if (EltVT == MVT::i64 || EltVT == MVT::f64) { V2EltIdx0 = 2; } else - LLVM_UNREACHABLE("Unhandled vector type in LowerVECTOR_SHUFFLE"); + llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE"); for (unsigned i = 0; i != MaxElts; ++i) { if (SVN->getMaskElt(i) < 0) @@ -1834,7 +1834,7 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { // Create a constant vector: switch (Op.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected constant value type in " + default: llvm_unreachable("Unexpected constant value type in " "LowerSCALAR_TO_VECTOR"); case MVT::v16i8: n_copies = 16; VT = MVT::i8; break; case MVT::v8i16: n_copies = 8; VT = MVT::i16; break; @@ -1853,7 +1853,7 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { } else { // Otherwise, copy the value from one register to another: switch (Op0.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected value type in LowerSCALAR_TO_VECTOR"); + default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR"); case MVT::i8: case MVT::i16: case MVT::i32: @@ -1880,13 +1880,13 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { // sanity checks: if (VT == MVT::i8 && EltNo >= 16) - LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15"); + llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15"); else if (VT == MVT::i16 && EltNo >= 8) - LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7"); + llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7"); else if (VT == MVT::i32 && EltNo >= 4) - LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4"); + llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4"); else if (VT == MVT::i64 && EltNo >= 2) - LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2"); + llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2"); if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) { // i32 and i64: Element 0 is the preferred slot @@ -2065,7 +2065,7 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, assert(Op.getValueType() == MVT::i8); switch (Opc) { default: - LLVM_UNREACHABLE("Unhandled i8 math operator"); + llvm_unreachable("Unhandled i8 math operator"); /*NOTREACHED*/ break; case ISD::ADD: { @@ -2585,7 +2585,7 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) cerr << "*Op.getNode():\n"; Op.getNode()->dump(); #endif - llvm_unreachable(); + llvm_unreachable(0); } case ISD::LOAD: case ISD::EXTLOAD: diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index eba1ca127c..26a4241819 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -314,7 +314,7 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } else if (RC == SPU::VECREGRegisterClass) { opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8; } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); @@ -347,7 +347,7 @@ void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } else if (RC == SPU::VECREGRegisterClass) { /* Opc = PPC::STVX; */ } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) @@ -383,7 +383,7 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, } else if (RC == SPU::VECREGRegisterClass) { opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8; } else { - LLVM_UNREACHABLE("Unknown regclass in loadRegFromStackSlot!"); + llvm_unreachable("Unknown regclass in loadRegFromStackSlot!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); @@ -420,7 +420,7 @@ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, } else if (RC == SPU::GPRCRegisterClass) { /* Opc = something else! */ } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp index 162e9fd12c..9ebbf00dbc 100644 --- a/lib/Target/CppBackend/CPPBackend.cpp +++ b/lib/Target/CppBackend/CPPBackend.cpp @@ -325,7 +325,7 @@ namespace { void CppWriter::printVisibilityType(GlobalValue::VisibilityTypes VisType) { switch (VisType) { - default: LLVM_UNREACHABLE("Unknown GVar visibility"); + default: llvm_unreachable("Unknown GVar visibility"); case GlobalValue::DefaultVisibility: Out << "GlobalValue::DefaultVisibility"; break; @@ -844,7 +844,7 @@ namespace { printConstant(CE->getOperand(0)); Out << "Constant* " << constName << " = ConstantExpr::getCast("; switch (CE->getOpcode()) { - default: LLVM_UNREACHABLE("Invalid cast opcode"); + default: llvm_unreachable("Invalid cast opcode"); case Instruction::Trunc: Out << "Instruction::Trunc"; break; case Instruction::ZExt: Out << "Instruction::ZExt"; break; case Instruction::SExt: Out << "Instruction::SExt"; break; diff --git a/lib/Target/DarwinTargetAsmInfo.cpp b/lib/Target/DarwinTargetAsmInfo.cpp index 609497638a..0b6babe53b 100644 --- a/lib/Target/DarwinTargetAsmInfo.cpp +++ b/lib/Target/DarwinTargetAsmInfo.cpp @@ -152,7 +152,7 @@ DarwinTargetAsmInfo::SelectSectionForGlobal(const GlobalValue *GV) const { ConstDataCoalSection: MergeableConstSection(cast<GlobalVariable>(GV))); default: - LLVM_UNREACHABLE("Unsuported section kind for global"); + llvm_unreachable("Unsuported section kind for global"); } // FIXME: Do we have any extra special weird cases? @@ -212,6 +212,6 @@ DarwinTargetAsmInfo::SelectSectionForMachineConst(const Type *Ty) const { std::string DarwinTargetAsmInfo::UniqueSectionForGlobal(const GlobalValue* GV, SectionKind::Kind kind) const { - LLVM_UNREACHABLE("Darwin does not use unique sections"); + llvm_unreachable("Darwin does not use unique sections"); return ""; } diff --git a/lib/Target/ELFTargetAsmInfo.cpp b/lib/Target/ELFTargetAsmInfo.cpp index b513a604c0..752f4757dd 100644 --- a/lib/Target/ELFTargetAsmInfo.cpp +++ b/lib/Target/ELFTargetAsmInfo.cpp @@ -75,7 +75,7 @@ ELFTargetAsmInfo::SelectSectionForGlobal(const GlobalValue *GV) const { if (const Function *F = dyn_cast<Function>(GV)) { switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::PrivateLinkage: case Function::InternalLinkage: case Function::DLLExportLinkage: @@ -124,11 +124,11 @@ ELFTargetAsmInfo::SelectSectionForGlobal(const GlobalValue *GV) const { case SectionKind::ThreadBSS: return TLSBSSSection; default: - LLVM_UNREACHABLE("Unsuported section kind for global"); + llvm_unreachable("Unsuported section kind for global"); } } } else - LLVM_UNREACHABLE("Unsupported global"); + llvm_unreachable("Unsupported global"); return NULL; } diff --git a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp index 111749e778..e7ed64e5c8 100644 --- a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp +++ b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp @@ -318,13 +318,13 @@ void IA64AsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::PrivateLinkage: break; case GlobalValue::GhostLinkage: - LLVM_UNREACHABLE("GhostLinkage cannot appear in IA64AsmPrinter!"); + llvm_unreachable("GhostLinkage cannot appear in IA64AsmPrinter!"); case GlobalValue::DLLImportLinkage: - LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!"); + llvm_unreachable("DLLImport linkage is not supported by this target!"); case GlobalValue::DLLExportLinkage: - LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!"); + llvm_unreachable("DLLExport linkage is not supported by this target!"); default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index adb4c4b5fb..fc24241a6c 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -215,7 +215,7 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) { if(isFP) { // if this is an FP divide, we finish up here and exit early if(isModulus) - LLVM_UNREACHABLE("Sorry, try another FORTRAN compiler."); + llvm_unreachable("Sorry, try another FORTRAN compiler."); SDValue TmpE2, TmpY3, TmpQ0, TmpR0; @@ -406,7 +406,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { APFloat(+1.0f) : APFloat(+1.0))) { V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64); } else - LLVM_UNREACHABLE("Unexpected FP constant!"); + llvm_unreachable("Unexpected FP constant!"); ReplaceUses(SDValue(N, 0), V); return 0; @@ -468,7 +468,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { #ifndef NDEBUG N->dump(CurDAG); #endif - LLVM_UNREACHABLE("Cannot load this type!"); + llvm_unreachable("Cannot load this type!"); case MVT::i1: { // this is a bool Opc = IA64::LD1; // first we load a byte, then compare for != 0 if(N->getValueType(0) == MVT::i1) { // XXX: early exit! @@ -504,7 +504,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { unsigned Opc; if (ISD::isNON_TRUNCStore(N)) { switch (N->getOperand(1).getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("unknown type in store"); + default: llvm_unreachable("unknown type in store"); case MVT::i1: { // this is a bool Opc = IA64::ST1; // we store either 0 or 1 as a byte // first load zero! @@ -524,7 +524,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { } } else { // Truncating store switch(ST->getMemoryVT().getSimpleVT()) { - default: LLVM_UNREACHABLE("unknown type in truncstore"); + default: llvm_unreachable("unknown type in truncstore"); case MVT::i8: Opc = IA64::ST1; break; case MVT::i16: Opc = IA64::ST2; break; case MVT::i32: Opc = IA64::ST4; break; diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index 8e675eba9a..587860c5b5 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -194,7 +194,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, switch (getValueType(I->getType()).getSimpleVT()) { default: - LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg."); + llvm_unreachable("ERROR in LowerArgs: can't lower this type of arg."); case MVT::f32: // fixme? (well, will need to for weird FP structy stuff, // see intel ABI docs) @@ -298,7 +298,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, // Finally, inform the code generator which regs we return values in. // (see the ISD::RET: case in the instruction selector) switch (getValueType(F.getReturnType()).getSimpleVT()) { - default: LLVM_UNREACHABLE("i have no idea where to return this type!"); + default: llvm_unreachable("i have no idea where to return this type!"); case MVT::isVoid: break; case MVT::i1: case MVT::i8: @@ -362,7 +362,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, SDValue ValToStore(0, 0), ValToConvert(0, 0); unsigned ObjSize=8; switch (ObjectVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("unexpected argument type!"); + default: llvm_unreachable("unexpected argument type!"); case MVT::i1: case MVT::i8: case MVT::i16: @@ -493,7 +493,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, if (InFlag.getNode()) CallOperands.push_back(InFlag); else - LLVM_UNREACHABLE("this should never happen!"); + llvm_unreachable("this should never happen!"); // to make way for a hack: Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys, @@ -516,7 +516,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, SDValue RetVal; if (RetTyVT != MVT::isVoid) { switch (RetTyVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unknown value type to return!"); + default: llvm_unreachable("Unknown value type to return!"); case MVT::i1: { // bools are just like other integers (returned in r8) // we *could* fall through to the truncate below, but this saves a // few redundant predicate ops @@ -573,15 +573,15 @@ SDValue IA64TargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Should not custom lower this!"); + default: llvm_unreachable("Should not custom lower this!"); case ISD::GlobalTLSAddress: - LLVM_UNREACHABLE("TLS not implemented for IA64."); + llvm_unreachable("TLS not implemented for IA64."); case ISD::RET: { SDValue AR_PFSVal, Copy; switch(Op.getNumOperands()) { default: - LLVM_UNREACHABLE("Do not know how to return this many arguments!"); + llvm_unreachable("Do not know how to return this many arguments!"); case 1: AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64); AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS, diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp index 5f53d7d804..2a1411ae68 100644 --- a/lib/Target/IA64/IA64InstrInfo.cpp +++ b/lib/Target/IA64/IA64InstrInfo.cpp @@ -113,7 +113,7 @@ void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addFrameIndex(FrameIdx) .addReg(IA64::r2); } else - LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg" + llvm_unreachable("sorry, I don't know how to store this sort of reg" "in the stack"); } @@ -130,7 +130,7 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } else if (RC == IA64::PRRegisterClass) { Opc = IA64::ST1; } else { - LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg"); + llvm_unreachable("sorry, I don't know how to store this sort of reg"); } DebugLoc DL = DebugLoc::getUnknownLoc(); @@ -164,7 +164,7 @@ void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, .addReg(IA64::r2) .addReg(IA64::r0); } else { - LLVM_UNREACHABLE("sorry, I don't know how to load this sort of reg" + llvm_unreachable("sorry, I don't know how to load this sort of reg" "from the stack"); } } @@ -181,7 +181,7 @@ void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, } else if (RC == IA64::PRRegisterClass) { Opc = IA64::LD1; } else { - LLVM_UNREACHABLE("sorry, I don't know how to load this sort of reg"); + llvm_unreachable("sorry, I don't know how to load this sort of reg"); } DebugLoc DL = DebugLoc::getUnknownLoc(); diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index a1a7574c84..6e3471dab3 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -293,7 +293,7 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF, } unsigned IA64RegisterInfo::getRARegister() const { - LLVM_UNREACHABLE("What is the return address register"); + llvm_unreachable("What is the return address register"); return 0; } @@ -302,17 +302,17 @@ unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const { } unsigned IA64RegisterInfo::getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned IA64RegisterInfo::getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("What is the dwarf register number"); + llvm_unreachable("What is the dwarf register number"); return -1; } diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp index 0fdbbf1adc..591c37107d 100644 --- a/lib/Target/MSIL/MSILWriter.cpp +++ b/lib/Target/MSIL/MSILWriter.cpp @@ -292,7 +292,7 @@ std::string MSILWriter::getConvModopt(unsigned CallingConvID) { return "modopt([mscorlib]System.Runtime.CompilerServices.CallConvStdcall) "; default: cerr << "CallingConvID = " << CallingConvID << '\n'; - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); } return ""; // Not reached } @@ -338,7 +338,7 @@ std::string MSILWriter::getPrimitiveTypeName(const Type* Ty, bool isSigned) { return "float64 "; default: cerr << "Type = " << *Ty << '\n'; - LLVM_UNREACHABLE("Invalid primitive type"); + llvm_unreachable("Invalid primitive type"); } return ""; // Not reached } @@ -366,7 +366,7 @@ std::string MSILWriter::getTypeName(const Type* Ty, bool isSigned, return "valuetype '"+getArrayTypeName(Ty->getTypeID(),Ty)+"' "; default: cerr << "Type = " << *Ty << '\n'; - LLVM_UNREACHABLE("Invalid type in getTypeName()"); + llvm_unreachable("Invalid type in getTypeName()"); } return ""; // Not reached } @@ -410,7 +410,7 @@ std::string MSILWriter::getTypePostfix(const Type* Ty, bool Expand, return "i"+utostr(TD->getTypeAllocSize(Ty)); default: cerr << "TypeID = " << Ty->getTypeID() << '\n'; - LLVM_UNREACHABLE("Invalid type in TypeToPostfix()"); + llvm_unreachable("Invalid type in TypeToPostfix()"); } return ""; // Not reached } @@ -425,7 +425,7 @@ void MSILWriter::printConvToPtr() { printSimpleInstruction("conv.u8"); break; default: - LLVM_UNREACHABLE("Module use not supporting pointer size"); + llvm_unreachable("Module use not supporting pointer size"); } } @@ -437,14 +437,14 @@ void MSILWriter::printPtrLoad(uint64_t N) { // FIXME: Need overflow test? if (!isUInt32(N)) { cerr << "Value = " << utostr(N) << '\n'; - LLVM_UNREACHABLE("32-bit pointer overflowed"); + llvm_unreachable("32-bit pointer overflowed"); } break; case Module::Pointer64: printSimpleInstruction("ldc.i8",utostr(N).c_str()); break; default: - LLVM_UNREACHABLE("Module use not supporting pointer size"); + llvm_unreachable("Module use not supporting pointer size"); } } @@ -480,7 +480,7 @@ void MSILWriter::printConstLoad(const Constant* C) { printPtrLoad(0); } else { cerr << "Constant = " << *C << '\n'; - LLVM_UNREACHABLE("Invalid constant value"); + llvm_unreachable("Invalid constant value"); } Out << '\n'; } @@ -529,7 +529,7 @@ void MSILWriter::printValueLoad(const Value* V) { break; default: cerr << "Value = " << *V << '\n'; - LLVM_UNREACHABLE("Invalid value location"); + llvm_unreachable("Invalid value location"); } } @@ -544,7 +544,7 @@ void MSILWriter::printValueSave(const Value* V) { break; default: cerr << "Value = " << *V << '\n'; - LLVM_UNREACHABLE("Invalid value location"); + llvm_unreachable("Invalid value location"); } } @@ -705,7 +705,7 @@ void MSILWriter::printCastInstruction(unsigned int Op, const Value* V, break; default: cerr << "Opcode = " << Op << '\n'; - LLVM_UNREACHABLE("Invalid conversion instruction"); + llvm_unreachable("Invalid conversion instruction"); } } @@ -796,7 +796,7 @@ void MSILWriter::printFunctionCall(const Value* FnVal, Name = getConvModopt(Invoke->getCallingConv()); else { cerr << "Instruction = " << Inst->getName() << '\n'; - LLVM_UNREACHABLE("Need \"Invoke\" or \"Call\" instruction only"); + llvm_unreachable("Need \"Invoke\" or \"Call\" instruction only"); } if (const Function* F = dyn_cast<Function>(FnVal)) { // Direct call. @@ -844,7 +844,7 @@ void MSILWriter::printIntrinsicCall(const IntrinsicInst* Inst) { break; default: cerr << "Intrinsic ID = " << Inst->getIntrinsicID() << '\n'; - LLVM_UNREACHABLE("Invalid intrinsic function"); + llvm_unreachable("Invalid intrinsic function"); } } @@ -908,7 +908,7 @@ void MSILWriter::printICmpInstruction(unsigned Predicate, const Value* Left, break; default: cerr << "Predicate = " << Predicate << '\n'; - LLVM_UNREACHABLE("Invalid icmp predicate"); + llvm_unreachable("Invalid icmp predicate"); } } @@ -1002,7 +1002,7 @@ void MSILWriter::printFCmpInstruction(unsigned Predicate, const Value* Left, printSimpleInstruction("or"); break; default: - LLVM_UNREACHABLE("Illegal FCmp predicate"); + llvm_unreachable("Illegal FCmp predicate"); } } @@ -1199,10 +1199,10 @@ void MSILWriter::printInstruction(const Instruction* Inst) { printAllocaInstruction(cast<AllocaInst>(Inst)); break; case Instruction::Malloc: - LLVM_UNREACHABLE("LowerAllocationsPass used"); + llvm_unreachable("LowerAllocationsPass used"); break; case Instruction::Free: - LLVM_UNREACHABLE("LowerAllocationsPass used"); + llvm_unreachable("LowerAllocationsPass used"); break; case Instruction::Unreachable: printSimpleInstruction("ldstr", "\"Unreachable instruction\""); @@ -1215,7 +1215,7 @@ void MSILWriter::printInstruction(const Instruction* Inst) { break; default: cerr << "Instruction = " << Inst->getName() << '\n'; - LLVM_UNREACHABLE("Unsupported instruction"); + llvm_unreachable("Unsupported instruction"); } } @@ -1403,7 +1403,7 @@ void MSILWriter::printConstantExpr(const ConstantExpr* CE) { break; default: cerr << "Expression = " << *CE << "\n"; - LLVM_UNREACHABLE("Invalid constant expression"); + llvm_unreachable("Invalid constant expression"); } } @@ -1437,7 +1437,7 @@ void MSILWriter::printStaticInitializerList() { printSimpleInstruction(postfix.c_str()); } else { cerr << "Constant = " << *I->constant << '\n'; - LLVM_UNREACHABLE("Invalid static initializer"); + llvm_unreachable("Invalid static initializer"); } } } @@ -1501,7 +1501,7 @@ unsigned int MSILWriter::getBitWidth(const Type* Ty) { return N; default: cerr << "Bits = " << N << '\n'; - LLVM_UNREACHABLE("Unsupported integer width"); + llvm_unreachable("Unsupported integer width"); } return 0; // Not reached } @@ -1558,12 +1558,12 @@ void MSILWriter::printStaticConstant(const Constant* C, uint64_t& Offset) { // Null pointer initialization if (TySize==4) Out << "int32 (0)"; else if (TySize==8) Out << "int64 (0)"; - else LLVM_UNREACHABLE("Invalid pointer size"); + else llvm_unreachable("Invalid pointer size"); } break; default: cerr << "TypeID = " << Ty->getTypeID() << '\n'; - LLVM_UNREACHABLE("Invalid type in printStaticConstant()"); + llvm_unreachable("Invalid type in printStaticConstant()"); } // Increase offset. Offset += TySize; @@ -1586,7 +1586,7 @@ void MSILWriter::printStaticInitializer(const Constant* C, break; default: cerr << "Type = " << *C << "\n"; - LLVM_UNREACHABLE("Invalid constant type"); + llvm_unreachable("Invalid constant type"); } // Print initializer std::string label = Name; diff --git a/lib/Target/MSP430/MSP430AsmPrinter.cpp b/lib/Target/MSP430/MSP430AsmPrinter.cpp index 0f711abc4f..b6eb6fef56 100644 --- a/lib/Target/MSP430/MSP430AsmPrinter.cpp +++ b/lib/Target/MSP430/MSP430AsmPrinter.cpp @@ -100,7 +100,7 @@ void MSP430AsmPrinter::emitFunctionHeader(const MachineFunction &MF) { EmitAlignment(FnAlign, F); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::InternalLinkage: // Symbols default to internal. case Function::PrivateLinkage: break; @@ -162,7 +162,7 @@ void MSP430AsmPrinter::printMachineInstruction(const MachineInstr *MI) { if (printInstruction(MI)) return; - LLVM_UNREACHABLE("Should not happen"); + llvm_unreachable("Should not happen"); } void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, @@ -207,7 +207,7 @@ void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, return; } default: - LLVM_UNREACHABLE("Not implemented yet!"); + llvm_unreachable("Not implemented yet!"); } } @@ -231,7 +231,7 @@ void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, printOperand(MI, OpNum); } } else - LLVM_UNREACHABLE("Unsupported memory operand"); + llvm_unreachable("Unsupported memory operand"); } void MSP430AsmPrinter::printCCOperand(const MachineInstr *MI, int OpNum) { @@ -239,7 +239,7 @@ void MSP430AsmPrinter::printCCOperand(const MachineInstr *MI, int OpNum) { switch (CC) { default: - LLVM_UNREACHABLE("Unsupported CC code"); + llvm_unreachable("Unsupported CC code"); break; case MSP430::COND_E: O << "eq"; diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp index 69d9caea94..219f4374a8 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -123,7 +123,7 @@ SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); default: - LLVM_UNREACHABLE("unimplemented operand"); + llvm_unreachable("unimplemented operand"); return SDValue(); } } @@ -144,7 +144,7 @@ SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); switch (CC) { default: - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); case CallingConv::C: case CallingConv::Fast: return LowerCCCArguments(Op, DAG); @@ -156,7 +156,7 @@ SDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { unsigned CallingConv = TheCall->getCallingConv(); switch (CallingConv) { default: - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); case CallingConv::Fast: case CallingConv::C: return LowerCCCCallTo(Op, DAG, CallingConv); @@ -197,7 +197,7 @@ SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op, cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " << RegVT.getSimpleVT() << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } case MVT::i16: unsigned VReg = @@ -331,7 +331,7 @@ SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); @@ -516,7 +516,7 @@ static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, unsigned &TargetCC, // FIXME: Handle jump negative someday TargetCC = MSP430::COND_INVALID; switch (CC) { - default: LLVM_UNREACHABLE("Invalid integer condition!"); + default: llvm_unreachable("Invalid integer condition!"); case ISD::SETEQ: TargetCC = MSP430::COND_E; // aka COND_Z break; diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp index 8dc71df7b1..37fbb6d999 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -45,7 +45,7 @@ void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addFrameIndex(FrameIdx).addImm(0) .addReg(SrcReg, getKillRegState(isKill)); else - LLVM_UNREACHABLE("Cannot store this register to stack slot!"); + llvm_unreachable("Cannot store this register to stack slot!"); } void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, @@ -62,7 +62,7 @@ void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, MI, DL, get(MSP430::MOV8rm)) .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0); else - LLVM_UNREACHABLE("Cannot store this register to stack slot!"); + llvm_unreachable("Cannot store this register to stack slot!"); } bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB, @@ -172,7 +172,7 @@ MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, // Conditional branch. unsigned Count = 0; - LLVM_UNREACHABLE("Implement conditional branches!"); + llvm_unreachable("Implement conditional branches!"); return Count; } diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp index 2c96f85aaf..6b2b555d41 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.cpp +++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -292,7 +292,7 @@ void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF, switch (RetOpcode) { case MSP430::RET: break; // These are ok default: - LLVM_UNREACHABLE("Can only insert epilog into returning blocks"); + llvm_unreachable("Can only insert epilog into returning blocks"); } // Get the number of bytes to allocate from the FrameInfo @@ -328,7 +328,7 @@ void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF, // mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); if (MFI->hasVarSizedObjects()) { - LLVM_UNREACHABLE("Not implemented yet!"); + llvm_unreachable("Not implemented yet!"); } else { // adjust stack pointer back: SPW += numbytes if (NumBytes) { @@ -350,7 +350,7 @@ unsigned MSP430RegisterInfo::getFrameRegister(MachineFunction &MF) const { } int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("Not implemented yet!"); + llvm_unreachable("Not implemented yet!"); return 0; } diff --git a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp index 9768710469..7a0e5e8ac3 100644 --- a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp @@ -216,7 +216,7 @@ emitCurrentABIString(void) default: break; } - LLVM_UNREACHABLE("Unknown Mips ABI"); + llvm_unreachable("Unknown Mips ABI"); return NULL; } @@ -406,7 +406,7 @@ printOperand(const MachineInstr *MI, int opNum) break; default: - LLVM_UNREACHABLE("<unknown operand type>"); + llvm_unreachable("<unknown operand type>"); } if (closeP) O << ")"; @@ -545,13 +545,13 @@ printModuleLevelGV(const GlobalVariable* GVar) { printSizeAndType = false; break; case GlobalValue::GhostLinkage: - LLVM_UNREACHABLE("Should not have any unmaterialized functions!"); + llvm_unreachable("Should not have any unmaterialized functions!"); case GlobalValue::DLLImportLinkage: - LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!"); + llvm_unreachable("DLLImport linkage is not supported by this target!"); case GlobalValue::DLLExportLinkage: - LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!"); + llvm_unreachable("DLLExport linkage is not supported by this target!"); default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index f3fa17938b..0b10c9aee2 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -248,7 +248,7 @@ static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) { switch(BC) { default: - LLVM_UNREACHABLE("Unknown branch code"); + llvm_unreachable("Unknown branch code"); case Mips::BRANCH_T : return Mips::BC1T; case Mips::BRANCH_F : return Mips::BC1F; case Mips::BRANCH_TL : return Mips::BC1TL; @@ -258,7 +258,7 @@ static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) { static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown fp condition code!"); + default: llvm_unreachable("Unknown fp condition code!"); case ISD::SETEQ: case ISD::SETOEQ: return Mips::FCOND_EQ; case ISD::SETUNE: return Mips::FCOND_OGL; @@ -542,14 +542,14 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); } - LLVM_UNREACHABLE("Dont know how to handle GlobalAddress"); + llvm_unreachable("Dont know how to handle GlobalAddress"); return SDValue(0,0); } SDValue MipsTargetLowering:: LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { - LLVM_UNREACHABLE("TLS not implemented for MIPS."); + llvm_unreachable("TLS not implemented for MIPS."); return SDValue(); // Not reached } @@ -753,7 +753,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG) // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: if (Subtarget->isABI_O32() && VA.isRegLoc()) { if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) @@ -978,7 +978,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) if (!Subtarget->isSingleFloat()) RC = Mips::AFGR64RegisterClass; } else - LLVM_UNREACHABLE("RegVT not supported by FORMAL_ARGUMENTS Lowering"); + llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); // Transform the arguments stored on // physical registers into virtual ones @@ -1140,7 +1140,7 @@ LowerRET(SDValue Op, SelectionDAG &DAG) unsigned Reg = MipsFI->getSRetReturnReg(); if (!Reg) - LLVM_UNREACHABLE("sret virtual register not created in the entry block"); + llvm_unreachable("sret virtual register not created in the entry block"); SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 1150765822..34b5a6ee8f 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -373,7 +373,7 @@ static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc) unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Illegal condition code!"); + default: llvm_unreachable("Illegal condition code!"); case Mips::COND_E : return Mips::BEQ; case Mips::COND_NE : return Mips::BNE; case Mips::COND_GZ : return Mips::BGTZ; @@ -422,7 +422,7 @@ unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC) Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Illegal condition code!"); + default: llvm_unreachable("Illegal condition code!"); case Mips::COND_E : return Mips::COND_NE; case Mips::COND_NE : return Mips::COND_E; case Mips::COND_GZ : return Mips::COND_LEZ; diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index 9c47d8e0d5..1fb678f333 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -93,7 +93,7 @@ namespace Mips { inline static const char *MipsFCCToString(Mips::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code"); + default: llvm_unreachable("Unknown condition code"); case FCOND_F: case FCOND_T: return "f"; case FCOND_UN: diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index 816d7c7980..c7aea693cd 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -80,7 +80,7 @@ getRegisterNumbering(unsigned RegEnum) case Mips::SP : case Mips::F29: return 29; case Mips::FP : case Mips::F30: case Mips::D15: return 30; case Mips::RA : case Mips::F31: return 31; - default: LLVM_UNREACHABLE("Unknown register number!"); + default: llvm_unreachable("Unknown register number!"); } return 0; // Not reached } @@ -516,19 +516,19 @@ getFrameRegister(MachineFunction &MF) const { unsigned MipsRegisterInfo:: getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned MipsRegisterInfo:: getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } int MipsRegisterInfo:: getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("What is the dwarf register number"); + llvm_unreachable("What is the dwarf register number"); return -1; } diff --git a/lib/Target/PIC16/PIC16.h b/lib/Target/PIC16/PIC16.h index 6af4664b84..3b6fcee4a2 100644 --- a/lib/Target/PIC16/PIC16.h +++ b/lib/Target/PIC16/PIC16.h @@ -308,7 +308,7 @@ namespace PIC16CC { inline static const char *PIC16CondCodeToString(PIC16CC::CondCodes CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code"); + default: llvm_unreachable("Unknown condition code"); case PIC16CC::NE: return "ne"; case PIC16CC::EQ: return "eq"; case PIC16CC::LT: return "lt"; @@ -324,7 +324,7 @@ namespace PIC16CC { inline static bool isSignedComparison(PIC16CC::CondCodes CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code"); + default: llvm_unreachable("Unknown condition code"); case PIC16CC::NE: case PIC16CC::EQ: case PIC16CC::LT: diff --git a/lib/Target/PIC16/PIC16AsmPrinter.cpp b/lib/Target/PIC16/PIC16AsmPrinter.cpp index d80476cdfa..b6401df287 100644 --- a/lib/Target/PIC16/PIC16AsmPrinter.cpp +++ b/lib/Target/PIC16/PIC16AsmPrinter.cpp @@ -128,7 +128,7 @@ void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << TM.getRegisterInfo()->get(MO.getReg()).AsmName; else - LLVM_UNREACHABLE("not implemented"); + llvm_unreachable("not implemented"); return; case MachineOperand::MO_Immediate: @@ -155,7 +155,7 @@ void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { return; default: - LLVM_UNREACHABLE(" Operand type not supported."); + llvm_unreachable(" Operand type not supported."); } } diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index c8c353f911..9a3d70461f 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -1228,7 +1228,7 @@ SDValue PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { // return should have odd number of operands if ((Op.getNumOperands() % 2) == 0 ) { - LLVM_UNREACHABLE("Do not know how to return this many arguments!"); + llvm_unreachable("Do not know how to return this many arguments!"); } // Number of values to return @@ -1697,7 +1697,7 @@ SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N, static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code!"); + default: llvm_unreachable("Unknown condition code!"); case ISD::SETNE: return PIC16CC::NE; case ISD::SETEQ: return PIC16CC::EQ; case ISD::SETGT: return PIC16CC::GT; diff --git a/lib/Target/PIC16/PIC16InstrInfo.cpp b/lib/Target/PIC16/PIC16InstrInfo.cpp index dad0266b7b..cb0c41bc0b 100644 --- a/lib/Target/PIC16/PIC16InstrInfo.cpp +++ b/lib/Target/PIC16/PIC16InstrInfo.cpp @@ -105,7 +105,7 @@ void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addImm(1); // Emit banksel for it. } else - LLVM_UNREACHABLE("Can't store this register to stack slot"); + llvm_unreachable("Can't store this register to stack slot"); } void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, @@ -145,7 +145,7 @@ void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, .addImm(1); // Emit banksel for it. } else - LLVM_UNREACHABLE("Can't load this register from stack slot"); + llvm_unreachable("Can't load this register from stack slot"); } bool PIC16InstrInfo::copyRegToReg (MachineBasicBlock &MBB, diff --git a/lib/Target/PIC16/PIC16RegisterInfo.cpp b/lib/Target/PIC16/PIC16RegisterInfo.cpp index bb4f278cbf..bbdb353665 100644 --- a/lib/Target/PIC16/PIC16RegisterInfo.cpp +++ b/lib/Target/PIC16/PIC16RegisterInfo.cpp @@ -65,17 +65,17 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const int PIC16RegisterInfo:: getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("Not keeping track of debug information yet!!"); + llvm_unreachable("Not keeping track of debug information yet!!"); return -1; } unsigned PIC16RegisterInfo::getFrameRegister(MachineFunction &MF) const { - LLVM_UNREACHABLE("PIC16 Does not have any frame register"); + llvm_unreachable("PIC16 Does not have any frame register"); return 0; } unsigned PIC16RegisterInfo::getRARegister() const { - LLVM_UNREACHABLE("PIC16 Does not have any return address register"); + llvm_unreachable("PIC16 Does not have any return address register"); return 0; } diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp index cec32739bc..fddc1c2993 100644 --- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp @@ -71,7 +71,7 @@ namespace { unsigned enumRegToMachineReg(unsigned enumReg) { switch (enumReg) { - default: LLVM_UNREACHABLE("Unhandled register!"); + default: llvm_unreachable("Unhandled register!"); case PPC::CR0: return 0; case PPC::CR1: return 1; case PPC::CR2: return 2; @@ -81,7 +81,7 @@ namespace { case PPC::CR6: return 6; case PPC::CR7: return 7; } - llvm_unreachable(); + llvm_unreachable(0); } /// printInstruction - This method is automatically generated by tablegen @@ -349,7 +349,7 @@ namespace { void PPCAsmPrinter::printOp(const MachineOperand &MO) { switch (MO.getType()) { case MachineOperand::MO_Immediate: - LLVM_UNREACHABLE("printOp() does not handle immediate values"); + llvm_unreachable("printOp() does not handle immediate values"); case MachineOperand::MO_MachineBasicBlock: printBasicBlockLabel(MO.getMBB()); @@ -551,7 +551,7 @@ void PPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) { if (printInstruction(MI)) return; // Printer was automatically generated - LLVM_UNREACHABLE("Unhandled instruction in asm writer!"); + llvm_unreachable("Unhandled instruction in asm writer!"); } /// runOnMachineFunction - This uses the printMachineInstruction() @@ -571,7 +571,7 @@ bool PPCLinuxAsmPrinter::runOnMachineFunction(MachineFunction &MF) { SwitchToSection(TAI->SectionForGlobal(F)); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::PrivateLinkage: case Function::InternalLinkage: // Symbols default to internal. break; @@ -706,7 +706,7 @@ void PPCLinuxAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::PrivateLinkage: break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); @@ -748,7 +748,7 @@ bool PPCDarwinAsmPrinter::runOnMachineFunction(MachineFunction &MF) { SwitchToSection(TAI->SectionForGlobal(F)); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::PrivateLinkage: case Function::InternalLinkage: // Symbols default to internal. break; @@ -936,7 +936,7 @@ void PPCDarwinAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::PrivateLinkage: break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index 4943e5c8e1..4090a22805 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -181,7 +181,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, assert(MovePCtoLROffset && "MovePCtoLR not seen yet?"); } switch (MI.getOpcode()) { - default: MI.dump(); LLVM_UNREACHABLE("Unknown instruction for relocation!"); + default: MI.dump(); llvm_unreachable("Unknown instruction for relocation!"); case PPC::LIS: case PPC::LIS8: case PPC::ADDIS: @@ -268,7 +268,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, #ifndef NDEBUG cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } return rv; diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index 244d3954af..e754d9d5a5 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -142,7 +142,7 @@ getHazardType(SUnit *SU) { return Hazard; switch (InstrType) { - default: LLVM_UNREACHABLE("Unknown instruction type!"); + default: llvm_unreachable("Unknown instruction type!"); case PPCII::PPC970_FXU: case PPCII::PPC970_LSU: case PPCII::PPC970_FPU: @@ -168,7 +168,7 @@ getHazardType(SUnit *SU) { if (isLoad && NumStores) { unsigned LoadSize; switch (Opcode) { - default: LLVM_UNREACHABLE("Unknown load!"); + default: llvm_unreachable("Unknown load!"); case PPC::LBZ: case PPC::LBZU: case PPC::LBZX: case PPC::LBZ8: case PPC::LBZU8: @@ -236,7 +236,7 @@ void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { if (isStore) { unsigned ThisStoreSize; switch (Opcode) { - default: LLVM_UNREACHABLE("Unknown store instruction!"); + default: llvm_unreachable("Unknown store instruction!"); case PPC::STB: case PPC::STB8: case PPC::STBU: case PPC::STBU8: case PPC::STBX: case PPC::STBX8: diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index b17e54dd5a..922135571f 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -602,8 +602,8 @@ static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { case ISD::SETONE: case ISD::SETOLE: case ISD::SETOGE: - LLVM_UNREACHABLE("Should be lowered by legalize!"); - default: LLVM_UNREACHABLE("Unknown condition!"); + llvm_unreachable("Should be lowered by legalize!"); + default: llvm_unreachable("Unknown condition!"); case ISD::SETOEQ: case ISD::SETEQ: return PPC::PRED_EQ; case ISD::SETUNE: @@ -634,7 +634,7 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { Invert = false; Other = -1; switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition!"); + default: llvm_unreachable("Unknown condition!"); case ISD::SETOLT: case ISD::SETLT: return 0; // Bit #0 = SETOLT case ISD::SETOGT: @@ -653,7 +653,7 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { case ISD::SETOGE: case ISD::SETOLE: case ISD::SETONE: - LLVM_UNREACHABLE("Invalid branch code: should be expanded by legalize"); + llvm_unreachable("Invalid branch code: should be expanded by legalize"); // These are invalid for floating point. Assume integer. case ISD::SETULT: return 0; case ISD::SETUGT: return 1; @@ -941,7 +941,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { // Handle PPC32 integer and normal FP loads. assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); switch (LoadedVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Invalid PPC load type!"); + default: llvm_unreachable("Invalid PPC load type!"); case MVT::f64: Opcode = PPC::LFDU; break; case MVT::f32: Opcode = PPC::LFSU; break; case MVT::i32: Opcode = PPC::LWZU; break; @@ -953,7 +953,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); switch (LoadedVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Invalid PPC load type!"); + default: llvm_unreachable("Invalid PPC load type!"); case MVT::i64: Opcode = PPC::LDU; break; case MVT::i32: Opcode = PPC::LWZU8; break; case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; @@ -970,7 +970,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { PPCLowering.getPointerTy(), MVT::Other, Ops, 3); } else { - LLVM_UNREACHABLE("R+R preindex loads not supported yet!"); + llvm_unreachable("R+R preindex loads not supported yet!"); } } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 842361fe97..5cabf04542 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1156,7 +1156,7 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { - LLVM_UNREACHABLE("TLS not implemented for PPC."); + llvm_unreachable("TLS not implemented for PPC."); return SDValue(); // Not reached } @@ -1251,7 +1251,7 @@ SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget) { - LLVM_UNREACHABLE("VAARG not yet implemented for the SVR4 ABI!"); + llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!"); return SDValue(); // Not reached } @@ -1544,7 +1544,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS_SVR4(SDValue Op, switch (ValVT.getSimpleVT()) { default: - LLVM_UNREACHABLE("ValVT not supported by FORMAL_ARGUMENTS Lowering"); + llvm_unreachable("ValVT not supported by FORMAL_ARGUMENTS Lowering"); case MVT::i32: RC = PPC::GPRCRegisterClass; break; @@ -1785,7 +1785,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS_Darwin(SDValue Op, } switch(ObjectVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unhandled argument type!"); + default: llvm_unreachable("Unhandled argument type!"); case MVT::i32: case MVT::f32: VecArgOffset += isPPC64 ? 8 : 4; @@ -1892,7 +1892,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS_Darwin(SDValue Op, } switch (ObjectVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unhandled argument type!"); + default: llvm_unreachable("Unhandled argument type!"); case MVT::i32: if (!isPPC64) { if (GPR_idx != Num_GPR_Regs) { @@ -2591,7 +2591,7 @@ SDValue PPCTargetLowering::LowerCALL_SVR4(SDValue Op, SelectionDAG &DAG, cerr << "Call operand #" << i << " has unhandled type " << ArgVT.getMVTString() << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } } else { @@ -2902,7 +2902,7 @@ SDValue PPCTargetLowering::LowerCALL_Darwin(SDValue Op, SelectionDAG &DAG, } switch (Arg.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ValueType for argument!"); + default: llvm_unreachable("Unexpected ValueType for argument!"); case MVT::i32: case MVT::i64: if (GPR_idx != NumGPRs) { @@ -3309,7 +3309,7 @@ SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDValue Tmp; switch (Op.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unhandled FP_TO_INT type in custom expander!"); + default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); case MVT::i32: Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : PPCISD::FCTIDZ, @@ -3795,7 +3795,7 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, int ShufIdxs[16]; switch (OpNum) { - default: LLVM_UNREACHABLE("Unknown i32 permute!"); + default: llvm_unreachable("Unknown i32 permute!"); case OP_VMRGHW: ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; @@ -4147,7 +4147,7 @@ SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { } return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); } else { - LLVM_UNREACHABLE("Unknown mul to lower!"); + llvm_unreachable("Unknown mul to lower!"); } } @@ -4155,7 +4155,7 @@ SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { /// SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Wasn't expecting to be able to lower this!"); + default: llvm_unreachable("Wasn't expecting to be able to lower this!"); case ISD::ConstantPool: return LowerConstantPool(Op, DAG); case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); @@ -4817,7 +4817,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, BB = exitMBB; BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); } else { - LLVM_UNREACHABLE("Unexpected instr type to insert"); + llvm_unreachable("Unexpected instr type to insert"); } F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. @@ -5192,7 +5192,7 @@ void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter, if (!CST) return; // Must be an immediate to match. unsigned Value = CST->getZExtValue(); switch (Letter) { - default: LLVM_UNREACHABLE("Unknown constraint letter!"); + default: llvm_unreachable("Unknown constraint letter!"); case 'I': // "I" is a signed 16-bit constant. if ((short)Value == (int)Value) Result = DAG.getTargetConstant(Value, Op.getValueType()); diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 63adf329f4..8b5e4b2cf9 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -487,7 +487,7 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, .addReg(PPC::R0) .addReg(PPC::R0)); } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } return false; @@ -538,7 +538,7 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } else if (RC == PPC::VRRCRegisterClass) { Opc = PPC::STVX; } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, getKillRegState(isKill)); @@ -634,7 +634,7 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) .addReg(PPC::R0)); } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } } @@ -676,7 +676,7 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, } else if (RC == PPC::VRRCRegisterClass) { Opc = PPC::LVX; } else { - LLVM_UNREACHABLE("Unknown regclass!"); + llvm_unreachable("Unknown regclass!"); } DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); diff --git a/lib/Target/PowerPC/PPCJITInfo.cpp b/lib/Target/PowerPC/PPCJITInfo.cpp index 91deca1ef3..ef25d92f71 100644 --- a/lib/Target/PowerPC/PPCJITInfo.cpp +++ b/lib/Target/PowerPC/PPCJITInfo.cpp @@ -199,7 +199,7 @@ asm( ); #else void PPC32CompilationCallback() { - LLVM_UNREACHABLE("This is not a power pc, you can't execute this!"); + llvm_unreachable("This is not a power pc, you can't execute this!"); } #endif @@ -265,7 +265,7 @@ asm( ); #else void PPC64CompilationCallback() { - LLVM_UNREACHABLE("This is not a power pc, you can't execute this!"); + llvm_unreachable("This is not a power pc, you can't execute this!"); } #endif @@ -383,7 +383,7 @@ void PPCJITInfo::relocate(void *Function, MachineRelocation *MR, unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4; intptr_t ResultPtr = (intptr_t)MR->getResultPointer(); switch ((PPC::RelocationType)MR->getRelocationType()) { - default: LLVM_UNREACHABLE("Unknown relocation type!"); + default: llvm_unreachable("Unknown relocation type!"); case PPC::reloc_pcrel_bx: // PC-relative relocation for b and bl instructions. ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2; diff --git a/lib/Target/PowerPC/PPCMachOWriterInfo.cpp b/lib/Target/PowerPC/PPCMachOWriterInfo.cpp index 9e57bd952d..4c14454096 100644 --- a/lib/Target/PowerPC/PPCMachOWriterInfo.cpp +++ b/lib/Target/PowerPC/PPCMachOWriterInfo.cpp @@ -47,9 +47,9 @@ unsigned PPCMachOWriterInfo::GetTargetRelocation(MachineRelocation &MR, Addr = (uintptr_t)MR.getResultPointer() + ToAddr; switch ((PPC::RelocationType)MR.getRelocationType()) { - default: LLVM_UNREACHABLE("Unknown PPC relocation type!"); + default: llvm_unreachable("Unknown PPC relocation type!"); case PPC::reloc_absolute_low_ix: - LLVM_UNREACHABLE("Unhandled PPC relocation type!"); + llvm_unreachable("Unhandled PPC relocation type!"); break; case PPC::reloc_vanilla: { diff --git a/lib/Target/PowerPC/PPCPredicates.cpp b/lib/Target/PowerPC/PPCPredicates.cpp index bb9e16606a..12bb0a1434 100644 --- a/lib/Target/PowerPC/PPCPredicates.cpp +++ b/lib/Target/PowerPC/PPCPredicates.cpp @@ -18,7 +18,7 @@ using namespace llvm; PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { switch (Opcode) { - default: LLVM_UNREACHABLE("Unknown PPC branch opcode!"); + default: llvm_unreachable("Unknown PPC branch opcode!"); case PPC::PRED_EQ: return PPC::PRED_NE; case PPC::PRED_NE: return PPC::PRED_EQ; case PPC::PRED_LT: return PPC::PRED_GE; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 6f807fe90b..6016eb461e 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -113,7 +113,7 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { case R30: case X30: case F30: case V30: case CR7EQ: return 30; case R31: case X31: case F31: case V31: case CR7UN: return 31; default: - LLVM_UNREACHABLE("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); + llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); } } @@ -1065,7 +1065,7 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) MinVR = Reg; } } else { - LLVM_UNREACHABLE("Unknown RegisterClass!"); + llvm_unreachable("Unknown RegisterClass!"); } } diff --git a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp index 04e1cc8bb6..e01ce7259b 100644 --- a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp @@ -185,7 +185,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { << MO.getIndex(); break; default: - LLVM_UNREACHABLE("<unknown operand type>"); + llvm_unreachable("<unknown operand type>"); } if (CloseParen) O << ")"; } @@ -299,13 +299,13 @@ void SparcAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::InternalLinkage: break; case GlobalValue::GhostLinkage: - LLVM_UNREACHABLE("Should not have any unmaterialized functions!"); + llvm_unreachable("Should not have any unmaterialized functions!"); case GlobalValue::DLLImportLinkage: - LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!"); + llvm_unreachable("DLLImport linkage is not supported by this target!"); case GlobalValue::DLLExportLinkage: - LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!"); + llvm_unreachable("DLLExport linkage is not supported by this target!"); default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp index 0f251de6a8..8ac459a161 100644 --- a/lib/Target/Sparc/FPMover.cpp +++ b/lib/Target/Sparc/FPMover.cpp @@ -76,7 +76,7 @@ static void getDoubleRegPair(unsigned DoubleReg, unsigned &EvenReg, OddReg = OddHalvesOfPairs[i]; return; } - LLVM_UNREACHABLE("Can't find reg"); + llvm_unreachable("Can't find reg"); } /// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB. @@ -109,7 +109,7 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) { else if (MI->getOpcode() == SP::FpABSD) MI->setDesc(TII->get(SP::FABSS)); else - LLVM_UNREACHABLE("Unknown opcode!"); + llvm_unreachable("Unknown opcode!"); MI->getOperand(0).setReg(EvenDestReg); MI->getOperand(1).setReg(EvenSrcReg); diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h index 539e50adde..82bc7e708d 100644 --- a/lib/Target/Sparc/Sparc.h +++ b/lib/Target/Sparc/Sparc.h @@ -84,7 +84,7 @@ namespace llvm { inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition code"); + default: llvm_unreachable("Unknown condition code"); case SPCC::ICC_NE: return "ne"; case SPCC::ICC_E: return "e"; case SPCC::ICC_G: return "g"; diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 4f5060ed99..3705ecb41e 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -99,7 +99,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, MVT ObjectVT = getValueType(I->getType()); switch (ObjectVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unhandled argument type!"); + default: llvm_unreachable("Unhandled argument type!"); case MVT::i1: case MVT::i8: case MVT::i16: @@ -252,7 +252,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { unsigned ArgsSize = 0; for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) { switch (TheCall->getArg(i).getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unknown value type!"); + default: llvm_unreachable("Unknown value type!"); case MVT::i1: case MVT::i8: case MVT::i16: @@ -290,7 +290,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); @@ -332,7 +332,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { SDValue ValToStore(0, 0); unsigned ObjSize; switch (ObjectVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unhandled argument type!"); + default: llvm_unreachable("Unhandled argument type!"); case MVT::i32: ObjSize = 4; @@ -498,7 +498,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { /// condition. static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown integer condition code!"); + default: llvm_unreachable("Unknown integer condition code!"); case ISD::SETEQ: return SPCC::ICC_E; case ISD::SETNE: return SPCC::ICC_NE; case ISD::SETLT: return SPCC::ICC_L; @@ -516,7 +516,7 @@ static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { /// FCC condition. static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Unknown fp condition code!"); + default: llvm_unreachable("Unknown fp condition code!"); case ISD::SETEQ: case ISD::SETOEQ: return SPCC::FCC_E; case ISD::SETNE: @@ -902,12 +902,12 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { SDValue SparcTargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Should not custom lower this!"); + default: llvm_unreachable("Should not custom lower this!"); // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: return SDValue(); case ISD::FRAMEADDR: return SDValue(); case ISD::GlobalTLSAddress: - LLVM_UNREACHABLE("TLS not implemented for Sparc."); + llvm_unreachable("TLS not implemented for Sparc."); case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); case ISD::ConstantPool: return LowerCONSTANTPOOL(Op, DAG); case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); @@ -931,7 +931,7 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, DebugLoc dl = MI->getDebugLoc(); // Figure out the conditional branch opcode to use for this select_cc. switch (MI->getOpcode()) { - default: LLVM_UNREACHABLE("Unknown SELECT_CC!"); + default: llvm_unreachable("Unknown SELECT_CC!"); case SP::SELECT_CC_Int_ICC: case SP::SELECT_CC_FP_ICC: case SP::SELECT_CC_DFP_ICC: diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 451c458ac0..af2a58a128 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -161,7 +161,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)); else - LLVM_UNREACHABLE("Can't store this register to stack slot"); + llvm_unreachable("Can't store this register to stack slot"); } void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -178,7 +178,7 @@ void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else if (RC == SP::DFPRegsRegisterClass) Opc = SP::STDFri; else - LLVM_UNREACHABLE("Can't load this register"); + llvm_unreachable("Can't load this register"); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB.addOperand(Addr[i]); @@ -201,7 +201,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, else if (RC == SP::DFPRegsRegisterClass) BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); else - LLVM_UNREACHABLE("Can't load this register from stack slot"); + llvm_unreachable("Can't load this register from stack slot"); } void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, @@ -216,7 +216,7 @@ void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, else if (RC == SP::DFPRegsRegisterClass) Opc = SP::LDDFri; else - LLVM_UNREACHABLE("Can't load this register"); + llvm_unreachable("Can't load this register"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index ab3c25e343..2acce3d15b 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -169,27 +169,27 @@ void SparcRegisterInfo::emitEpilogue(MachineFunction &MF, } unsigned SparcRegisterInfo::getRARegister() const { - LLVM_UNREACHABLE("What is the return address register"); + llvm_unreachable("What is the return address register"); return 0; } unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const { - LLVM_UNREACHABLE("What is the frame register"); + llvm_unreachable("What is the frame register"); return SP::G1; } unsigned SparcRegisterInfo::getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned SparcRegisterInfo::getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("What is the dwarf register number"); + llvm_unreachable("What is the dwarf register number"); return -1; } diff --git a/lib/Target/TargetAsmInfo.cpp b/lib/Target/TargetAsmInfo.cpp index 08ae2cf13e..eeebc27ec2 100644 --- a/lib/Target/TargetAsmInfo.cpp +++ b/lib/Target/TargetAsmInfo.cpp @@ -278,7 +278,7 @@ TargetAsmInfo::SectionFlagsForGlobal(const GlobalValue *GV, Flags |= SectionFlags::Small; break; default: - LLVM_UNREACHABLE("Unexpected section kind!"); + llvm_unreachable("Unexpected section kind!"); } if (GV->isWeakForLinker()) @@ -388,7 +388,7 @@ TargetAsmInfo::UniqueSectionForGlobal(const GlobalValue* GV, case SectionKind::ThreadBSS: return ".gnu.linkonce.tb." + GV->getName(); default: - LLVM_UNREACHABLE("Unknown section kind"); + llvm_unreachable("Unknown section kind"); } return NULL; } diff --git a/lib/Target/TargetData.cpp b/lib/Target/TargetData.cpp index b3f2e98f63..3f1979bc29 100644 --- a/lib/Target/TargetData.cpp +++ b/lib/Target/TargetData.cpp @@ -454,7 +454,7 @@ uint64_t TargetData::getTypeSizeInBits(const Type *Ty) const { case Type::VectorTyID: return cast<VectorType>(Ty)->getBitWidth(); default: - LLVM_UNREACHABLE("TargetData::getTypeSizeInBits(): Unsupported type"); + llvm_unreachable("TargetData::getTypeSizeInBits(): Unsupported type"); break; } return 0; @@ -509,7 +509,7 @@ unsigned char TargetData::getAlignment(const Type *Ty, bool abi_or_pref) const { AlignType = VECTOR_ALIGN; break; default: - LLVM_UNREACHABLE("Bad type for getAlignment!!!"); + llvm_unreachable("Bad type for getAlignment!!!"); break; } diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp index f160bd08e7..c726ccc57e 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp @@ -55,7 +55,7 @@ void X86ATTAsmPrinter::PrintPICBaseSymbol() const { else if (Subtarget->isTargetELF()) O << ".Lllvm$" << getFunctionNumber() << ".$piclabel"; else - LLVM_UNREACHABLE("Don't know how to print PIC label!"); + llvm_unreachable("Don't know how to print PIC label!"); } /// PrintUnmangledNameSafely - Print out the printable characters in the name. @@ -155,7 +155,7 @@ void X86ATTAsmPrinter::decorateName(std::string &Name, } break; default: - LLVM_UNREACHABLE("Unsupported DecorationStyle"); + llvm_unreachable("Unsupported DecorationStyle"); } } @@ -167,7 +167,7 @@ void X86ATTAsmPrinter::emitFunctionHeader(const MachineFunction &MF) { SwitchToSection(TAI->SectionForGlobal(F)); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::InternalLinkage: // Symbols default to internal. case Function::PrivateLinkage: EmitAlignment(FnAlign, F); @@ -292,7 +292,7 @@ bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) { /// which print to a label with various suffixes for relocation types etc. void X86ATTAsmPrinter::printSymbolOperand(const MachineOperand &MO) { switch (MO.getType()) { - default: LLVM_UNREACHABLE("unknown symbol type!"); + default: llvm_unreachable("unknown symbol type!"); case MachineOperand::MO_JumpTableIndex: O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_' << MO.getIndex(); @@ -366,7 +366,7 @@ void X86ATTAsmPrinter::printSymbolOperand(const MachineOperand &MO) { switch (MO.getTargetFlags()) { default: - LLVM_UNREACHABLE("Unknown target flag on GV operand"); + llvm_unreachable("Unknown target flag on GV operand"); case X86II::MO_NO_FLAG: // No flag. break; case X86II::MO_DARWIN_NONLAZY: @@ -404,7 +404,7 @@ void X86ATTAsmPrinter::printSymbolOperand(const MachineOperand &MO) { void X86ATTAsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo) { const MachineOperand &MO = MI->getOperand(OpNo); switch (MO.getType()) { - default: LLVM_UNREACHABLE("Unknown pcrel immediate operand"); + default: llvm_unreachable("Unknown pcrel immediate operand"); case MachineOperand::MO_Immediate: O << MO.getImm(); return; @@ -426,7 +426,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, const char *Modifier) { const MachineOperand &MO = MI->getOperand(OpNo); switch (MO.getType()) { - default: LLVM_UNREACHABLE("unknown operand type!"); + default: llvm_unreachable("unknown operand type!"); case MachineOperand::MO_Register: { assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && "Virtual registers should not make it this far!"); @@ -735,7 +735,7 @@ void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) { } else if (MO.isMBB()) { MCOp.MakeMBBLabel(getFunctionNumber(), MO.getMBB()->getNumber()); } else { - LLVM_UNREACHABLE("Unimp"); + llvm_unreachable("Unimp"); } TmpInst.addOperand(MCOp); @@ -887,7 +887,7 @@ void X86ATTAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::InternalLinkage: break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp index c3780d91f6..e0fa83a78b 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp @@ -28,7 +28,7 @@ using namespace llvm; void X86ATTAsmPrinter::printSSECC(const MCInst *MI, unsigned Op) { switch (MI->getOperand(Op).getImm()) { - default: LLVM_UNREACHABLE("Invalid ssecc argument!"); + default: llvm_unreachable("Invalid ssecc argument!"); case 0: O << "eq"; break; case 1: O << "lt"; break; case 2: O << "le"; break; @@ -42,7 +42,7 @@ void X86ATTAsmPrinter::printSSECC(const MCInst *MI, unsigned Op) { void X86ATTAsmPrinter::printPICLabel(const MCInst *MI, unsigned Op) { - LLVM_UNREACHABLE("This is only used for MOVPC32r," + llvm_unreachable("This is only used for MOVPC32r," "should lower before asm printing!"); } @@ -61,7 +61,7 @@ void X86ATTAsmPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) { O << TAI->getPrivateGlobalPrefix() << "BB" << Op.getMBBLabelFunction() << '_' << Op.getMBBLabelBlock(); else - LLVM_UNREACHABLE("Unknown pcrel immediate operand"); + llvm_unreachable("Unknown pcrel immediate operand"); } @@ -104,7 +104,7 @@ void X86ATTAsmPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) O << DispVal; } else { - LLVM_UNREACHABLE("non-immediate displacement for LEA?"); + llvm_unreachable("non-immediate displacement for LEA?"); //assert(DispSpec.isGlobal() || DispSpec.isCPI() || // DispSpec.isJTI() || DispSpec.isSymbol()); //printOperand(MI, Op+3, "mem"); diff --git a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp index 793616e798..9890fddbec 100644 --- a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp @@ -115,7 +115,7 @@ void X86IntelAsmPrinter::decorateName(std::string &Name, break; default: - LLVM_UNREACHABLE("Unsupported DecorationStyle"); + llvm_unreachable("Unsupported DecorationStyle"); } } @@ -144,7 +144,7 @@ bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) { SwitchToTextSection("_text", F); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unsupported linkage type!"); + default: llvm_unreachable("Unsupported linkage type!"); case Function::PrivateLinkage: case Function::InternalLinkage: EmitAlignment(FnAlign); @@ -268,7 +268,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO, void X86IntelAsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo){ const MachineOperand &MO = MI->getOperand(OpNo); switch (MO.getType()) { - default: LLVM_UNREACHABLE("Unknown pcrel immediate operand"); + default: llvm_unreachable("Unknown pcrel immediate operand"); case MachineOperand::MO_Immediate: O << MO.getImm(); return; @@ -520,7 +520,7 @@ bool X86IntelAsmPrinter::doFinalization(Module &M) { SwitchToSection(TAI->getDataSection()); break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } if (!bCustomSegment) diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index acaeea33b1..30bbc5cc8e 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -335,7 +335,7 @@ void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp, unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word; emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj); } else { - LLVM_UNREACHABLE("Unknown value to relocate!"); + llvm_unreachable("Unknown value to relocate!"); } } @@ -478,7 +478,7 @@ void Emitter<CodeEmitter>::emitInstruction( case X86II::GS: MCE.emitByte(0x65); break; - default: LLVM_UNREACHABLE("Invalid segment!"); + default: llvm_unreachable("Invalid segment!"); case 0: break; // No segment override! } @@ -513,7 +513,7 @@ void Emitter<CodeEmitter>::emitInstruction( (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8) >> X86II::Op0Shift)); break; // Two-byte opcode prefix - default: LLVM_UNREACHABLE("Invalid prefix!"); + default: llvm_unreachable("Invalid prefix!"); case 0: break; // No prefix! } @@ -548,13 +548,13 @@ void Emitter<CodeEmitter>::emitInstruction( unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc); switch (Desc->TSFlags & X86II::FormMask) { - default: LLVM_UNREACHABLE("Unknown FormMask value in X86 MachineCodeEmitter!"); + default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!"); case X86II::Pseudo: // Remember the current PC offset, this is the PIC relocation // base address. switch (Opcode) { default: - LLVM_UNREACHABLE("psuedo instructions should be removed before code emission"); + llvm_unreachable("psuedo instructions should be removed before code emission"); break; case TargetInstrInfo::INLINEASM: { // We allow inline assembler nodes with empty bodies - they can @@ -620,7 +620,7 @@ void Emitter<CodeEmitter>::emitInstruction( } else emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc)); } else { - LLVM_UNREACHABLE("Unknown RawFrm operand!"); + llvm_unreachable("Unknown RawFrm operand!"); } } break; @@ -811,7 +811,7 @@ void Emitter<CodeEmitter>::emitInstruction( #ifndef NDEBUG cerr << "Cannot encode: " << MI << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } diff --git a/lib/Target/X86/X86ELFWriterInfo.cpp b/lib/Target/X86/X86ELFWriterInfo.cpp index 9be7021a49..a26fe8cd9b 100644 --- a/lib/Target/X86/X86ELFWriterInfo.cpp +++ b/lib/Target/X86/X86ELFWriterInfo.cpp @@ -43,7 +43,7 @@ unsigned X86ELFWriterInfo::getRelocationType(unsigned MachineRelTy) const { return R_X86_64_64; case X86::reloc_picrel_word: default: - LLVM_UNREACHABLE("unknown relocation type"); + llvm_unreachable("unknown relocation type"); } } else { switch(MachineRelTy) { @@ -54,7 +54,7 @@ unsigned X86ELFWriterInfo::getRelocationType(unsigned MachineRelTy) const { case X86::reloc_absolute_dword: case X86::reloc_picrel_word: default: - LLVM_UNREACHABLE("unknown relocation type"); + llvm_unreachable("unknown relocation type"); } } return 0; @@ -66,7 +66,7 @@ long int X86ELFWriterInfo::getAddendForRelTy(unsigned RelTy) const { case R_X86_64_PC32: return -4; break; default: - LLVM_UNREACHABLE("unknown x86 relocation type"); + llvm_unreachable("unknown x86 relocation type"); } } return 0; diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 2b3304d19c..11919d9b27 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -1319,7 +1319,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) { // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: { bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index c15e3487c6..14bffdc799 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -256,7 +256,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { case X86II::CompareFP: handleCompareFP(I); break; case X86II::CondMovFP: handleCondMovFP(I); break; case X86II::SpecialFP: handleSpecialFP(I); break; - default: LLVM_UNREACHABLE("Unknown FP Type!"); + default: llvm_unreachable("Unknown FP Type!"); } // Check to see if any of the values defined by this instruction are dead @@ -946,7 +946,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { MachineInstr *MI = I; DebugLoc dl = MI->getDebugLoc(); switch (MI->getOpcode()) { - default: LLVM_UNREACHABLE("Unknown SpecialFP instruction!"); + default: llvm_unreachable("Unknown SpecialFP instruction!"); case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type! case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type! case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type! diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 8aa627f8a7..296a4d3856 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -1462,7 +1462,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { bool isSigned = Opcode == ISD::SMUL_LOHI; if (!isSigned) switch (NVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported VT!"); + default: llvm_unreachable("Unsupported VT!"); case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break; case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break; case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break; @@ -1470,7 +1470,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { } else switch (NVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported VT!"); + default: llvm_unreachable("Unsupported VT!"); case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break; case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break; case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break; @@ -1479,7 +1479,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { unsigned LoReg, HiReg; switch (NVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported VT!"); + default: llvm_unreachable("Unsupported VT!"); case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break; @@ -1568,7 +1568,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { bool isSigned = Opcode == ISD::SDIVREM; if (!isSigned) switch (NVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported VT!"); + default: llvm_unreachable("Unsupported VT!"); case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break; case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break; case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break; @@ -1576,7 +1576,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { } else switch (NVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported VT!"); + default: llvm_unreachable("Unsupported VT!"); case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break; case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break; case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break; @@ -1586,7 +1586,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { unsigned LoReg, HiReg; unsigned ClrOpcode, SExtOpcode; switch (NVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported VT!"); + default: llvm_unreachable("Unsupported VT!"); case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; ClrOpcode = 0; diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 1e79c4dee5..a2fedaf924 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1426,7 +1426,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { } } } else { - LLVM_UNREACHABLE("Unknown argument type!"); + llvm_unreachable("Unknown argument type!"); } unsigned Reg = DAG.getMachineFunction().addLiveIn(VA.getLocReg(), RC); @@ -1721,7 +1721,7 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); @@ -2167,7 +2167,7 @@ static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, } switch (SetCCOpcode) { - default: LLVM_UNREACHABLE("Invalid integer condition!"); + default: llvm_unreachable("Invalid integer condition!"); case ISD::SETEQ: return X86::COND_E; case ISD::SETGT: return X86::COND_G; case ISD::SETGE: return X86::COND_GE; @@ -2207,7 +2207,7 @@ static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, // 1 | 0 | 0 | X == Y // 1 | 1 | 1 | unordered switch (SetCCOpcode) { - default: LLVM_UNREACHABLE("Condcode should be pre-legalized away"); + default: llvm_unreachable("Condcode should be pre-legalized away"); case ISD::SETUEQ: case ISD::SETEQ: return X86::COND_E; case ISD::SETOLT: // flipped @@ -4715,7 +4715,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { Subtarget->is64Bit()); } - LLVM_UNREACHABLE("Unreachable"); + llvm_unreachable("Unreachable"); return SDValue(); } @@ -5038,7 +5038,7 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { unsigned Opc; switch (DstTy.getSimpleVT()) { - default: LLVM_UNREACHABLE("Invalid FP_TO_SINT to lower!"); + default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; @@ -5461,7 +5461,7 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); } - LLVM_UNREACHABLE("Illegal FP comparison"); + llvm_unreachable("Illegal FP comparison"); } // Handle all other FP comparisons here. return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); @@ -6247,7 +6247,7 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { case Intrinsic::x86_mmx_psrai_d: NewIntNo = Intrinsic::x86_mmx_psra_d; break; - default: LLVM_UNREACHABLE("Impossible intrinsic"); // Can't reach here. + default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. } break; } @@ -6397,7 +6397,7 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, switch (CC) { default: - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); case CallingConv::C: case CallingConv::X86_StdCall: { // Pass 'nest' parameter in ECX. @@ -6646,7 +6646,7 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Unknown ovf instruction!"); + default: llvm_unreachable("Unknown ovf instruction!"); case ISD::SADDO: // A subtract of one will be selected as a INC. Note that INC doesn't // set CF, so we can't do this for UADDO. @@ -6768,7 +6768,7 @@ SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { /// SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Should not custom lower this!"); + default: llvm_unreachable("Should not custom lower this!"); case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); @@ -7616,7 +7616,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // Get the X86 opcode to use. unsigned Opc; switch (MI->getOpcode()) { - default: LLVM_UNREACHABLE("illegal opcode!"); + default: llvm_unreachable("illegal opcode!"); case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; @@ -8355,7 +8355,7 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, SDValue ValOp = N->getOperand(0); switch (N->getOpcode()) { default: - LLVM_UNREACHABLE("Unknown shift opcode!"); + llvm_unreachable("Unknown shift opcode!"); break; case ISD::SHL: if (VT == MVT::v2i64) diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 06e2b8dff0..6c06e58d03 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -1300,7 +1300,7 @@ X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { unsigned Opc; unsigned Size; switch (MI->getOpcode()) { - default: LLVM_UNREACHABLE("Unreachable!"); + default: llvm_unreachable("Unreachable!"); case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; @@ -1455,7 +1455,7 @@ static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Illegal condition code!"); + default: llvm_unreachable("Illegal condition code!"); case X86::COND_E: return X86::JE; case X86::COND_NE: return X86::JNE; case X86::COND_L: return X86::JL; @@ -1479,7 +1479,7 @@ unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { /// e.g. turning COND_E to COND_NE. X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Illegal condition code!"); + default: llvm_unreachable("Illegal condition code!"); case X86::COND_E: return X86::COND_NE; case X86::COND_NE: return X86::COND_E; case X86::COND_L: return X86::COND_GE; @@ -1885,7 +1885,7 @@ static unsigned getStoreRegOpcode(unsigned SrcReg, } else if (RC == &X86::VR64RegClass) { Opc = X86::MMX_MOVQ64mr; } else { - LLVM_UNREACHABLE("Unknown regclass"); + llvm_unreachable("Unknown regclass"); } return Opc; @@ -1977,7 +1977,7 @@ static unsigned getLoadRegOpcode(unsigned DestReg, } else if (RC == &X86::VR64RegClass) { Opc = X86::MMX_MOVQ64rm; } else { - LLVM_UNREACHABLE("Unknown regclass"); + llvm_unreachable("Unknown regclass"); } return Opc; @@ -2645,7 +2645,7 @@ unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) { case X86II::Imm16: return 2; case X86II::Imm32: return 4; case X86II::Imm64: return 8; - default: LLVM_UNREACHABLE("Immediate size not set!"); + default: llvm_unreachable("Immediate size not set!"); return 0; } } @@ -2830,7 +2830,7 @@ static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) { } else if (RelocOp->isJTI()) { FinalSize += sizeJumpTableAddress(false); } else { - LLVM_UNREACHABLE("Unknown value to relocate!"); + llvm_unreachable("Unknown value to relocate!"); } return FinalSize; } @@ -2927,7 +2927,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI, case X86II::GS: ++FinalSize; break; - default: LLVM_UNREACHABLE("Invalid segment!"); + default: llvm_unreachable("Invalid segment!"); case 0: break; // No segment override! } @@ -2960,7 +2960,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI, case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: ++FinalSize; break; // Two-byte opcode prefix - default: LLVM_UNREACHABLE("Invalid prefix!"); + default: llvm_unreachable("Invalid prefix!"); case 0: break; // No prefix! } @@ -2994,7 +2994,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI, --NumOps; switch (Desc->TSFlags & X86II::FormMask) { - default: LLVM_UNREACHABLE("Unknown FormMask value in X86 MachineCodeEmitter!"); + default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!"); case X86II::Pseudo: // Remember the current PC offset, this is the PIC relocation // base address. @@ -3039,7 +3039,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI, } else if (MO.isImm()) { FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); } else { - LLVM_UNREACHABLE("Unknown RawFrm operand!"); + llvm_unreachable("Unknown RawFrm operand!"); } } break; diff --git a/lib/Target/X86/X86JITInfo.cpp b/lib/Target/X86/X86JITInfo.cpp index 4cc27efa1c..24e391ec17 100644 --- a/lib/Target/X86/X86JITInfo.cpp +++ b/lib/Target/X86/X86JITInfo.cpp @@ -322,7 +322,7 @@ extern "C" { #else // Not an i386 host void X86CompilationCallback() { - LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!"); + llvm_unreachable("Cannot call X86CompilationCallback() on a non-x86 arch!"); } #endif } @@ -554,7 +554,7 @@ char* X86JITInfo::allocateThreadLocalMemory(size_t size) { TLSOffset -= size; return TLSOffset; #else - LLVM_UNREACHABLE("Cannot allocate thread local storage on this arch!"); + llvm_unreachable("Cannot allocate thread local storage on this arch!"); return 0; #endif } diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 3ae758b7bf..437986fb9c 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -147,7 +147,7 @@ unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) { default: assert(isVirtualRegister(RegNo) && "Unknown physical register!"); - LLVM_UNREACHABLE("Register allocator hasn't allocated reg correctly yet!"); + llvm_unreachable("Register allocator hasn't allocated reg correctly yet!"); return 0; } } @@ -951,7 +951,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, case X86::TAILJMPr: case X86::TAILJMPm: break; // These are ok default: - LLVM_UNREACHABLE("Can only insert epilog into returning blocks"); + llvm_unreachable("Can only insert epilog into returning blocks"); } // Get the number of bytes to allocate from the FrameInfo @@ -1104,12 +1104,12 @@ void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) } unsigned X86RegisterInfo::getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned X86RegisterInfo::getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } diff --git a/lib/Target/X86/X86TargetAsmInfo.cpp b/lib/Target/X86/X86TargetAsmInfo.cpp index 5a60bce43d..c33b765316 100644 --- a/lib/Target/X86/X86TargetAsmInfo.cpp +++ b/lib/Target/X86/X86TargetAsmInfo.cpp @@ -283,7 +283,7 @@ X86COFFTargetAsmInfo::UniqueSectionForGlobal(const GlobalValue* GV, case SectionKind::RODataMergeStr: return ".rdata$linkonce" + GV->getName(); default: - LLVM_UNREACHABLE("Unknown section kind"); + llvm_unreachable("Unknown section kind"); } return NULL; } diff --git a/lib/Target/XCore/XCoreAsmPrinter.cpp b/lib/Target/XCore/XCoreAsmPrinter.cpp index 5234a9ba1f..5874294886 100644 --- a/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -204,13 +204,13 @@ emitGlobal(const GlobalVariable *GV) case GlobalValue::PrivateLinkage: break; case GlobalValue::GhostLinkage: - LLVM_UNREACHABLE("Should not have any unmaterialized functions!"); + llvm_unreachable("Should not have any unmaterialized functions!"); case GlobalValue::DLLImportLinkage: - LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!"); + llvm_unreachable("DLLImport linkage is not supported by this target!"); case GlobalValue::DLLExportLinkage: - LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!"); + llvm_unreachable("DLLExport linkage is not supported by this target!"); default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } EmitAlignment(Align, GV, 2); @@ -255,7 +255,7 @@ emitFunctionStart(MachineFunction &MF) O << "\t.cc_top " << CurrentFnName << ".function," << CurrentFnName << "\n"; switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::InternalLinkage: // Symbols default to internal. case Function::PrivateLinkage: break; @@ -358,7 +358,7 @@ void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << TM.getRegisterInfo()->get(MO.getReg()).AsmName; else - LLVM_UNREACHABLE("not implemented"); + llvm_unreachable("not implemented"); break; case MachineOperand::MO_Immediate: O << MO.getImm(); @@ -381,7 +381,7 @@ void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { << '_' << MO.getIndex(); break; default: - LLVM_UNREACHABLE("not implemented"); + llvm_unreachable("not implemented"); } } @@ -410,7 +410,7 @@ void XCoreAsmPrinter::printMachineInstruction(const MachineInstr *MI) { if (printInstruction(MI)) { return; } - LLVM_UNREACHABLE("Unhandled instruction in asm writer!"); + llvm_unreachable("Unhandled instruction in asm writer!"); } bool XCoreAsmPrinter::doInitialization(Module &M) { diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index c2cc09cc66..f6a181e640 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -167,7 +167,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) { case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); default: - LLVM_UNREACHABLE("unimplemented operand"); + llvm_unreachable("unimplemented operand"); return SDValue(); } } @@ -179,7 +179,7 @@ void XCoreTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { switch (N->getOpcode()) { default: - LLVM_UNREACHABLE("Don't know how to custom expand this!"); + llvm_unreachable("Don't know how to custom expand this!"); return; case ISD::ADD: case ISD::SUB: @@ -266,7 +266,7 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal()); } if (! GVar) { - LLVM_UNREACHABLE("Thread local object not a GlobalVariable?"); + llvm_unreachable("Thread local object not a GlobalVariable?"); return SDValue(); } const Type *Ty = cast<PointerType>(GV->getType())->getElementType(); @@ -275,7 +275,7 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) cerr << "Size of thread local object " << GVar->getName() << " is unknown\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } SDValue base = getGlobalAddressWrapper(GA, GV, DAG); const TargetData *TD = TM.getTargetData(); @@ -292,7 +292,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) // FIXME there isn't really debug info here DebugLoc dl = CP->getDebugLoc(); if (Subtarget.isXS1A()) { - LLVM_UNREACHABLE("Lowering of constant pool unimplemented"); + llvm_unreachable("Lowering of constant pool unimplemented"); return SDValue(); } else { MVT PtrVT = Op.getValueType(); @@ -356,7 +356,7 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG) SDValue XCoreTargetLowering:: LowerVAARG(SDValue Op, SelectionDAG &DAG) { - LLVM_UNREACHABLE("unimplemented"); + llvm_unreachable("unimplemented"); // FIX Arguments passed by reference need a extra dereference. SDNode *Node = Op.getNode(); DebugLoc dl = Node->getDebugLoc(); @@ -426,7 +426,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG) switch (CallingConv) { default: - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); case CallingConv::Fast: case CallingConv::C: return LowerCCCCallTo(Op, DAG, CallingConv); @@ -474,7 +474,7 @@ LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC) // Promote the value if needed. switch (VA.getLocInfo()) { - default: LLVM_UNREACHABLE("Unknown loc info!"); + default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); @@ -607,7 +607,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) switch(CC) { default: - LLVM_UNREACHABLE("Unsupported calling convention"); + llvm_unreachable("Unsupported calling convention"); case CallingConv::C: case CallingConv::Fast: return LowerCCCArguments(Op, DAG); @@ -655,7 +655,7 @@ LowerCCCArguments(SDValue Op, SelectionDAG &DAG) cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " << RegVT.getSimpleVT() << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } case MVT::i32: unsigned VReg = RegInfo.createVirtualRegister( diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index ea35504766..ad47ac2665 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -187,7 +187,7 @@ static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Illegal condition code!"); + default: llvm_unreachable("Illegal condition code!"); case XCore::COND_TRUE : return XCore::BRFT_lru6; case XCore::COND_FALSE : return XCore::BRFF_lru6; } @@ -198,7 +198,7 @@ static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) { switch (CC) { - default: LLVM_UNREACHABLE("Illegal condition code!"); + default: llvm_unreachable("Illegal condition code!"); case XCore::COND_TRUE : return XCore::COND_FALSE; case XCore::COND_FALSE : return XCore::COND_TRUE; } @@ -408,7 +408,7 @@ void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { - LLVM_UNREACHABLE("unimplemented"); + llvm_unreachable("unimplemented"); } void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, @@ -428,7 +428,7 @@ void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { - LLVM_UNREACHABLE("unimplemented"); + llvm_unreachable("unimplemented"); } bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index 7773064add..8bdfcdcdb5 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -148,7 +148,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, cerr << "eliminateCallFramePseudoInstr size too big: " << Amount << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } MachineInstr *New; @@ -257,7 +257,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, .addReg(ScratchReg, RegState::Kill); break; default: - LLVM_UNREACHABLE("Unexpected Opcode"); + llvm_unreachable("Unexpected Opcode"); } } else { switch (MI.getOpcode()) { @@ -278,7 +278,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, .addImm(Offset); break; default: - LLVM_UNREACHABLE("Unexpected Opcode"); + llvm_unreachable("Unexpected Opcode"); } } } else { @@ -309,7 +309,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, .addImm(Offset); break; default: - LLVM_UNREACHABLE("Unexpected Opcode"); + llvm_unreachable("Unexpected Opcode"); } } // Erase old instruction. |