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| author | Jan Vesely <jan.vesely@rutgers.edu> | 2014-06-18 12:27:17 +0000 |
|---|---|---|
| committer | Jan Vesely <jan.vesely@rutgers.edu> | 2014-06-18 12:27:17 +0000 |
| commit | c32d52df24505b29bc4f9385d701c5bcec594fad (patch) | |
| tree | d7206792b12b674a50d5e8f7594e42a8724996f7 /lib/Target | |
| parent | 2d06e73d88d8acb201622be5838ff2bac1b0a4c7 (diff) | |
| download | llvm-c32d52df24505b29bc4f9385d701c5bcec594fad.tar.gz llvm-c32d52df24505b29bc4f9385d701c5bcec594fad.tar.bz2 llvm-c32d52df24505b29bc4f9385d701c5bcec594fad.tar.xz | |
R600: Implement 64bit SRA
v2: Use capitalized variable name
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211159 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index ad5a82fcfe..f0e13e56d8 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -161,6 +161,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : // to be Legal/Custom in order to avoid library calls. setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); + setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); @@ -558,6 +559,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG); + case ISD::SRA_PARTS: case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG); case ISD::FCOS: case ISD::FSIN: return LowerTrig(Op, DAG); @@ -958,6 +960,8 @@ SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const { SDValue Zero = DAG.getConstant(0, VT); SDValue One = DAG.getConstant(1, VT); + const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; + SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT); SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT); SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); @@ -971,14 +975,12 @@ SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const { SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift); Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One); - // TODO: SRA support here - SDValue HiSmall = DAG.getNode(ISD::SRL, DL, VT, Hi, Shift); + SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift); LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow); - // TODO: SRA support here - SDValue LoBig = DAG.getNode(ISD::SRL, DL, VT, Hi, BigShift); - SDValue HiBig = Zero; + SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); + SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero; Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); |