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author | Tim Northover <tnorthover@apple.com> | 2014-03-11 10:48:52 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-03-11 10:48:52 +0000 |
commit | ca396e391e13d417605ebed06780d92c88f14a6b (patch) | |
tree | a984bbd50ef52c0ad3f0fd66b81d1021b072d16c /lib/Target | |
parent | fb411c8b8ce42689d42b0d8e3a871d81f86a7298 (diff) | |
download | llvm-ca396e391e13d417605ebed06780d92c88f14a6b.tar.gz llvm-ca396e391e13d417605ebed06780d92c88f14a6b.tar.bz2 llvm-ca396e391e13d417605ebed06780d92c88f14a6b.tar.xz |
IR: add a second ordering operand to cmpxhg for failure
The syntax for "cmpxchg" should now look something like:
cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic
where the second ordering argument gives the required semantics in the case
that no exchange takes place. It should be no stronger than the first ordering
constraint and cannot be either "release" or "acq_rel" (since no store will
have taken place).
rdar://problem/15996804
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203559 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 8 | ||||
-rw-r--r-- | lib/Target/CppBackend/CPPBackend.cpp | 8 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 1 |
3 files changed, 11 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 691961ef2a..aa7ca7f91f 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -6054,10 +6054,10 @@ ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results, Node->getOperand(i), DAG.getIntPtrConstant(1))); } SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); - SDValue Result = - DAG.getAtomic(Node->getOpcode(), dl, MVT::i64, Tys, Ops.data(), Ops.size(), - cast<MemSDNode>(Node)->getMemOperand(), AN->getOrdering(), - AN->getSynchScope()); + SDValue Result = DAG.getAtomic( + Node->getOpcode(), dl, MVT::i64, Tys, Ops.data(), Ops.size(), + cast<MemSDNode>(Node)->getMemOperand(), AN->getSuccessOrdering(), + AN->getFailureOrdering(), AN->getSynchScope()); SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) }; Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); Results.push_back(Result.getValue(2)); diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp index b13709914b..31585d9296 100644 --- a/lib/Target/CppBackend/CPPBackend.cpp +++ b/lib/Target/CppBackend/CPPBackend.cpp @@ -1567,12 +1567,16 @@ void CppWriter::printInstruction(const Instruction *I, } case Instruction::AtomicCmpXchg: { const AtomicCmpXchgInst *cxi = cast<AtomicCmpXchgInst>(I); - StringRef Ordering = ConvertAtomicOrdering(cxi->getOrdering()); + StringRef SuccessOrdering = + ConvertAtomicOrdering(cxi->getSuccessOrdering()); + StringRef FailureOrdering = + ConvertAtomicOrdering(cxi->getFailureOrdering()); StringRef CrossThread = ConvertAtomicSynchScope(cxi->getSynchScope()); Out << "AtomicCmpXchgInst* " << iName << " = new AtomicCmpXchgInst(" << opNames[0] << ", " << opNames[1] << ", " << opNames[2] << ", " - << Ordering << ", " << CrossThread << ", " << bbname + << SuccessOrdering << ", " << FailureOrdering << ", " + << CrossThread << ", " << bbname << ");"; nl(Out) << iName << "->setName(\""; printEscapedString(cxi->getName()); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 07c83e8b29..f651205bf3 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -13805,6 +13805,7 @@ static void ReplaceATOMIC_LOAD(SDNode *Node, Node->getOperand(1), Zero, Zero, cast<AtomicSDNode>(Node)->getMemOperand(), cast<AtomicSDNode>(Node)->getOrdering(), + cast<AtomicSDNode>(Node)->getOrdering(), cast<AtomicSDNode>(Node)->getSynchScope()); Results.push_back(Swap.getValue(0)); Results.push_back(Swap.getValue(1)); |