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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-09-13 19:56:38 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-09-13 19:56:38 +0000 |
| commit | dfb5935c76598cd19608e58bab55b9b611dab0b7 (patch) | |
| tree | bf6939e66f0a404d7513c278fa13833c016f8d76 /lib/Target | |
| parent | edca044ab872ca71085167b0e82ac29a4f335b6f (diff) | |
| download | llvm-dfb5935c76598cd19608e58bab55b9b611dab0b7.tar.gz llvm-dfb5935c76598cd19608e58bab55b9b611dab0b7.tar.bz2 llvm-dfb5935c76598cd19608e58bab55b9b611dab0b7.tar.xz | |
swap vselect operand order - pr10907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139630 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 6a08257360..fed7d35f02 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -5958,31 +5958,31 @@ defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem, let Predicates = [HasAVX] in { def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1), (v16i8 VR128:$src2))), - (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>; def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1), (v4i32 VR128:$src2))), - (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>; def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1), (v4f32 VR128:$src2))), - (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>; def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1), (v2i64 VR128:$src2))), - (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>; def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1), (v2f64 VR128:$src2))), - (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>; def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1), (v8i32 VR256:$src2))), - (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>; + (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>; def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1), (v8f32 VR256:$src2))), - (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>; + (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>; def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1), (v4i64 VR256:$src2))), - (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>; + (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>; def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1), (v4f64 VR256:$src2))), - (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>; + (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>; } /// SS41I_ternary_int - SSE 4.1 ternary operator @@ -6012,19 +6012,19 @@ defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>; let Predicates = [HasSSE41] in { def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1), (v16i8 VR128:$src2))), - (PBLENDVBrr0 VR128:$src1, VR128:$src2)>; + (PBLENDVBrr0 VR128:$src2, VR128:$src1)>; def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1), (v4i32 VR128:$src2))), - (BLENDVPSrr0 VR128:$src1, VR128:$src2)>; + (BLENDVPSrr0 VR128:$src2, VR128:$src1)>; def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1), (v4f32 VR128:$src2))), - (BLENDVPSrr0 VR128:$src1, VR128:$src2)>; + (BLENDVPSrr0 VR128:$src2, VR128:$src1)>; def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1), (v2i64 VR128:$src2))), - (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; + (BLENDVPDrr0 VR128:$src2, VR128:$src1)>; def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1), (v2f64 VR128:$src2))), - (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; + (BLENDVPDrr0 VR128:$src2, VR128:$src1)>; } let Predicates = [HasAVX] in |