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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-06-17 16:53:09 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-06-17 16:53:09 +0000 |
| commit | ff8dc48da387719d4b4c4712715be0e2d2672d87 (patch) | |
| tree | 0a56a8d12456af5b17e415f632ae90a7b9b6fc90 /lib/Target | |
| parent | bae98b1b454a86000d17d4df1abf072a8520b98f (diff) | |
| download | llvm-ff8dc48da387719d4b4c4712715be0e2d2672d87.tar.gz llvm-ff8dc48da387719d4b4c4712715be0e2d2672d87.tar.bz2 llvm-ff8dc48da387719d4b4c4712715be0e2d2672d87.tar.xz | |
R600/SI: Add a pattern for llvm.AMDGPU.barrier.global
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211109 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/R600/AMDGPUIntrinsics.td | 1 | ||||
| -rw-r--r-- | lib/Target/R600/EvergreenInstructions.td | 7 | ||||
| -rw-r--r-- | lib/Target/R600/SIInstructions.td | 9 |
3 files changed, 16 insertions, 1 deletions
diff --git a/lib/Target/R600/AMDGPUIntrinsics.td b/lib/Target/R600/AMDGPUIntrinsics.td index 95fab11a26..4ef23abfe3 100644 --- a/lib/Target/R600/AMDGPUIntrinsics.td +++ b/lib/Target/R600/AMDGPUIntrinsics.td @@ -65,6 +65,7 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in { def int_AMDGPU_bfe_u32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_AMDGPU_bfm : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_AMDGPU_barrier_local : Intrinsic<[], [], []>; + def int_AMDGPU_barrier_global : Intrinsic<[], [], []>; } // Legacy names for compatability. diff --git a/lib/Target/R600/EvergreenInstructions.td b/lib/Target/R600/EvergreenInstructions.td index 28725ff280..dcb7e982c7 100644 --- a/lib/Target/R600/EvergreenInstructions.td +++ b/lib/Target/R600/EvergreenInstructions.td @@ -348,7 +348,7 @@ def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; def GROUP_BARRIER : InstR600 < - (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local)], AnyALU>, + (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local), (int_AMDGPU_barrier_global)], AnyALU>, R600ALU_Word0, R600ALU_Word1_OP2 <0x54> { @@ -377,6 +377,11 @@ def GROUP_BARRIER : InstR600 < let ALUInst = 1; } +def : Pat < + (int_AMDGPU_barrier_global), + (GROUP_BARRIER) +>; + //===----------------------------------------------------------------------===// // LDS Instructions //===----------------------------------------------------------------------===// diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index be7d8a6d4a..2f04bea269 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1732,6 +1732,15 @@ def : Pat < >; //===----------------------------------------------------------------------===// +// SOPP Patterns +//===----------------------------------------------------------------------===// + +def : Pat < + (int_AMDGPU_barrier_global), + (S_BARRIER) +>; + +//===----------------------------------------------------------------------===// // VOP2 Patterns //===----------------------------------------------------------------------===// |