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authorDan Gohman <gohman@apple.com>2010-12-09 02:52:17 +0000
committerDan Gohman <gohman@apple.com>2010-12-09 02:52:17 +0000
commitd8e0c0438ab1ec86b2bd42da7a439caa7f0a61eb (patch)
treee40cb8e64fcdfcf9e8d257ff9cea52b233d2af89 /lib/Transforms/InstCombine/InstCombineShifts.cpp
parent1a48c032bd7c240fc4c52aee6dad57f8043a77d9 (diff)
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Really check that the bits that will become zero are actually already zero
before eliminating the operation that zeros them. This fixes rdar://8739316. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121353 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Transforms/InstCombine/InstCombineShifts.cpp')
-rw-r--r--lib/Transforms/InstCombine/InstCombineShifts.cpp3
1 files changed, 1 insertions, 2 deletions
diff --git a/lib/Transforms/InstCombine/InstCombineShifts.cpp b/lib/Transforms/InstCombine/InstCombineShifts.cpp
index e52f2013fe..e3232a491b 100644
--- a/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -168,9 +168,8 @@ static bool CanEvaluateShifted(Value *V, unsigned NumBits, bool isLeftShift,
// We can always turn lshr(c1)+shl(c2) -> lshr(c3)+and(c4), but it isn't
// profitable unless we know the and'd out bits are already zero.
if (CI->getZExtValue() > NumBits) {
- unsigned LowBits = CI->getZExtValue() - NumBits;
if (MaskedValueIsZero(I->getOperand(0),
- APInt::getLowBitsSet(TypeWidth, LowBits) << NumBits))
+ APInt::getLowBitsSet(TypeWidth, NumBits)))
return true;
}