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authorShuxin Yang <shuxin.llvm@gmail.com>2012-12-12 00:29:03 +0000
committerShuxin Yang <shuxin.llvm@gmail.com>2012-12-12 00:29:03 +0000
commit5f70c2e934c8cf7814fc047f4824ac89b35dd72d (patch)
tree3f4df3e7ca234645eda5b0d4143fb104a59016a1 /lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
parentc244f381768e2e6ab9daa807adbee18de4756a07 (diff)
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- Fix a problematic way in creating all-the-1 APInt.
- Propagate "exact" bit of [l|a]shr instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169942 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp')
-rw-r--r--lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 08aedb3200..13653183a7 100644
--- a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -858,8 +858,8 @@ Value *InstCombiner::SimplifyShrShlDemandedBits(Instruction *Shr,
Value *VarX = Shr->getOperand(0);
Type *Ty = VarX->getType();
- APInt BitMask1(Ty->getIntegerBitWidth(), (uint64_t)-1);
- APInt BitMask2(Ty->getIntegerBitWidth(), (uint64_t)-1);
+ APInt BitMask1(APInt::getAllOnesValue(Ty->getIntegerBitWidth()));
+ APInt BitMask2(APInt::getAllOnesValue(Ty->getIntegerBitWidth()));
bool isLshr = (Shr->getOpcode() == Instruction::LShr);
BitMask1 = isLshr ? (BitMask1.lshr(ShrAmt) << ShlAmt) :
@@ -891,6 +891,8 @@ Value *InstCombiner::SimplifyShrShlDemandedBits(Instruction *Shr,
Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt);
New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
BinaryOperator::CreateAShr(VarX, Amt);
+ if (cast<BinaryOperator>(Shr)->isExact())
+ New->setIsExact(true);
}
return InsertNewInstWith(New, *Shl);