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author | Eli Friedman <eli.friedman@gmail.com> | 2011-08-12 22:50:01 +0000 |
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committer | Eli Friedman <eli.friedman@gmail.com> | 2011-08-12 22:50:01 +0000 |
commit | f03bb260c90ad013aa4e55af36382875011c95b8 (patch) | |
tree | 6d554ebcc06bd6d3509a7808029994c894d002d3 /lib/VMCore/AsmWriter.cpp | |
parent | 10342123adec62151bf9060493dd13583c67ae52 (diff) | |
download | llvm-f03bb260c90ad013aa4e55af36382875011c95b8.tar.gz llvm-f03bb260c90ad013aa4e55af36382875011c95b8.tar.bz2 llvm-f03bb260c90ad013aa4e55af36382875011c95b8.tar.xz |
Move "atomic" and "volatile" designations on instructions after the opcode
of the instruction.
Note that this change affects the existing non-atomic load and store
instructions; the parser now accepts both forms, and the change is noted
in the release notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137527 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/VMCore/AsmWriter.cpp')
-rw-r--r-- | lib/VMCore/AsmWriter.cpp | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/lib/VMCore/AsmWriter.cpp b/lib/VMCore/AsmWriter.cpp index d166604113..1fc94ba7ca 100644 --- a/lib/VMCore/AsmWriter.cpp +++ b/lib/VMCore/AsmWriter.cpp @@ -1658,16 +1658,6 @@ void AssemblyWriter::printInstruction(const Instruction &I) { else Out << '%' << SlotNum << " = "; } - - // If this is an atomic load or store, print out the atomic marker. - if ((isa<LoadInst>(I) && cast<LoadInst>(I).isAtomic()) || - (isa<StoreInst>(I) && cast<StoreInst>(I).isAtomic())) - Out << "atomic "; - - // If this is a volatile load or store, print out the volatile marker. - if ((isa<LoadInst>(I) && cast<LoadInst>(I).isVolatile()) || - (isa<StoreInst>(I) && cast<StoreInst>(I).isVolatile())) - Out << "volatile "; if (isa<CallInst>(I) && cast<CallInst>(I).isTailCall()) Out << "tail "; @@ -1675,6 +1665,18 @@ void AssemblyWriter::printInstruction(const Instruction &I) { // Print out the opcode... Out << I.getOpcodeName(); + // If this is an atomic load or store, print out the atomic marker. + if ((isa<LoadInst>(I) && cast<LoadInst>(I).isAtomic()) || + (isa<StoreInst>(I) && cast<StoreInst>(I).isAtomic())) + Out << " atomic"; + + // If this is a volatile operation, print out the volatile marker. + if ((isa<LoadInst>(I) && cast<LoadInst>(I).isVolatile()) || + (isa<StoreInst>(I) && cast<StoreInst>(I).isVolatile()) || + (isa<AtomicCmpXchgInst>(I) && cast<AtomicCmpXchgInst>(I).isVolatile()) || + (isa<AtomicRMWInst>(I) && cast<AtomicRMWInst>(I).isVolatile())) + Out << " volatile"; + // Print out optimization information. WriteOptimizationInfo(Out, &I); |