Add support for a cycle counter intrinsic. As basically all processors have

this and have it in about the same form, I think this makes sense.
on X86, you do a RDTSC (64bit result, from any ring since the P5MMX)
on Alpha, you do a RDCC
on PPC, there is a sequence which may or may not work depending on how things
are setup by the OS.  Or something like that.  Maybe someone who knows PPC
can add support.  Something about the time base register.
on Sparc, you read %tick, which in some solaris versions (>=8) is readable by
userspace
on IA64 read ar.itc

So I think the ulong is justified since all of those are 64bit.
Support is slighly flaky on old chips (P5 and lower) and sometimes
depends on OS (PPC, Sparc).  But for modern OS/Hardware (aka this decade),
we should be ok.

I am still not sure what to do about lowering.  I can either see a lower to 0, to
gettimeofday (or the target os equivalent), or loudly complaining and refusing to
continue.

I am commiting an Alpha implementation.  I will add the X86 implementation if I
have to (I have use of it in the near future), but if someone who knows that
backend (and the funky multi-register results) better wants to add it, it would
take them a lot less time ;)

TODO: better lowering and legalizing, and support more platforms


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24299 91177308-0d34-0410-b5e6-96231b3b80d8

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