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authorMatheus Almeida <matheus.almeida@imgtec.com>2013-12-05 11:56:56 +0000
committerMatheus Almeida <matheus.almeida@imgtec.com>2013-12-05 11:56:56 +0000
commit00877e733fc0366a93240b85dccfbd853c6135c5 (patch)
treea0ef86b7e8fd3f950090c5fefa15904167bc4e18 /lib
parent4faa2b38fb0fa98fd3f157a5456c828c4e762dce (diff)
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[mips] Add some comments related to the optimization performed in performSELECTCombine.
The structure of the code was slightly modified so that the next patch is easier to read/review. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196496 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/Mips/MipsISelLowering.cpp29
1 files changed, 21 insertions, 8 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 1e8250c847..75ce59f1f8 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -535,19 +535,32 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
if (!FalseTy.isInteger())
return SDValue();
- ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
-
- if (!CN || CN->getZExtValue())
+ ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
+
+ // If the RHS (False) is 0, we swap the order of the operands
+ // of ISD::SELECT (obviously also inverting the condition) so that we can
+ // take advantage of conditional moves using the $0 register.
+ // Example:
+ // return (a != 0) ? x : 0;
+ // load $reg, x
+ // movz $reg, $0, a
+ if (!FalseC)
return SDValue();
const SDLoc DL(N);
- ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
- SDValue True = N->getOperand(1);
- SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
- SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
+ if (!FalseC->getZExtValue()) {
+ ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
+ SDValue True = N->getOperand(1);
+
+ SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
+ SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
- return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
+ return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
+ }
+
+ // Couldn't optimize.
+ return SDValue();
}
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,