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| author | Hal Finkel <hfinkel@anl.gov> | 2014-03-06 00:23:33 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2014-03-06 00:23:33 +0000 |
| commit | 025c1cefca00f262452c8c42717a4047b1836cd2 (patch) | |
| tree | 1990aa14403fa135fa0b928ebc83ecd954cc14ff /lib | |
| parent | 7cf97649660c15c81ce7dfdd4eed564297e15bde (diff) | |
| download | llvm-025c1cefca00f262452c8c42717a4047b1836cd2.tar.gz llvm-025c1cefca00f262452c8c42717a4047b1836cd2.tar.bz2 llvm-025c1cefca00f262452c8c42717a4047b1836cd2.tar.xz | |
When using CR bit registers on PPC32, handle the i1 vaarg case
When copying an i1 value into a GPR for a vaarg call, we need to explicitly
zero-extend the i1 value (otherwise an invalid CRBIT -> GPR copy will be
generated).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203041 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 05e74fb049..dce6051b18 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3773,6 +3773,9 @@ PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee, } if (VA.isRegLoc()) { + if (Arg.getValueType() == MVT::i1) + Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg); + seenFloatArg |= VA.getLocVT().isFloatingPoint(); // Put argument in a physical register. RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); |