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| author | Chris Lattner <sabre@nondot.org> | 2003-08-05 00:48:47 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2003-08-05 00:48:47 +0000 |
| commit | 02beda12214997e2ac9586781e1f8d377744e6fa (patch) | |
| tree | f2441dcc6147f62f2bea202b47cb748e059861f8 /lib | |
| parent | b10cea86a985d05786c60e6be641a93582ae6c29 (diff) | |
| download | llvm-02beda12214997e2ac9586781e1f8d377744e6fa.tar.gz llvm-02beda12214997e2ac9586781e1f8d377744e6fa.tar.bz2 llvm-02beda12214997e2ac9586781e1f8d377744e6fa.tar.xz | |
This is the real fix for the previous register allocator problem.
Physical registers should not float around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7587 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/InstSelectSimple.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86CodeEmitter.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelSimple.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 1 |
4 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 24c841d288..d66f7c225e 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -646,6 +646,8 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) { BuildMI(BB, SetCCOpcodeTab[0][OpNum], 0, X86::AL); BuildMI(BB, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1); BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL); + BuildMI(BB, X86::IMPLICIT_DEF, 0, X86::BH); + BuildMI(BB, X86::IMPLICIT_DEF, 0, X86::AH); BuildMI(BB, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX); // NOTE: visitSetCondInst knows that the value is dumped into the BL // register at this point for long values... diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 41289540ce..50b1faac8b 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -470,7 +470,7 @@ void Emitter::emitInstruction(MachineInstr &MI) { switch (Desc.TSFlags & X86II::FormMask) { default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!"); case X86II::Pseudo: - if (Opcode != X86::IMPLICIT_USE) + if (Opcode != X86::IMPLICIT_USE && Opcode != X86::IMPLICIT_DEF) std::cerr << "X86 Machine Code Emitter: No 'form', not emitting: " << MI; break; diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index 24c841d288..d66f7c225e 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -646,6 +646,8 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) { BuildMI(BB, SetCCOpcodeTab[0][OpNum], 0, X86::AL); BuildMI(BB, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1); BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL); + BuildMI(BB, X86::IMPLICIT_DEF, 0, X86::BH); + BuildMI(BB, X86::IMPLICIT_DEF, 0, X86::AH); BuildMI(BB, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX); // NOTE: visitSetCondInst knows that the value is dumped into the BL // register at this point for long values... diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index fd544670de..396464660a 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -107,6 +107,7 @@ def NOOP : X86Inst<"nop", 0x90, RawFrm, NoArg>; // nop def ADJCALLSTACKDOWN : X86Inst<"ADJCALLSTACKDOWN", 0, Pseudo, NoArg>; def ADJCALLSTACKUP : X86Inst<"ADJCALLSTACKUP", 0, Pseudo, NoArg>; def IMPLICIT_USE : X86Inst<"IMPLICIT_USE", 0, Pseudo, NoArg>; +def IMPLICIT_DEF : X86Inst<"IMPLICIT_DEF", 0, Pseudo, NoArg>; //===----------------------------------------------------------------------===// // Control Flow Instructions... |