Fix some typos and use type-based isel for VZIP/VUZP/VTRN

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79625 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 56 insertions, 56 deletions

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 3b394b0bf5..8d09549b2d 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1415,34 +1415,55 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
                             N->getOperand(4), N->getOperand(5), Chain };
     return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
   }
-  case ARMISD::VZIP16: {
-    EVT VT = N->getValueType(0);
-    return CurDAG->getTargetNode(ARM::VZIPd16, dl, VT, VT,
-                                 N->getOperand(0), N->getOperand(1));
-  }
-  case ARMISD::VZIP32: {
-    EVT VT = N->getValueType(0);
-    return CurDAG->getTargetNode(ARM::VZIPq32, dl, VT, VT,
-                                 N->getOperand(0), N->getOperand(1));
-  }
-  case ARMISD::VUZP16: {
-    EVT VT = N->getValueType(0);
-    return CurDAG->getTargetNode(ARM::VUZPd16, dl, VT, VT,
-                                 N->getOperand(0), N->getOperand(1));
-  }
-  case ARMISD::VUZP32: {
+  case ARMISD::VZIP: {
+    unsigned Opc = 0;
     EVT VT = N->getValueType(0);
-    return CurDAG->getTargetNode(ARM::VUZPq32, dl, VT, VT,
+    switch (VT.getSimpleVT().SimpleTy) {
+    default: return NULL;
+    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
+    case MVT::v4i16: Opc = ARM::VZIPd16; break;
+    case MVT::v2f32:
+    case MVT::v2i32: Opc = ARM::VZIPd32; break;
+    case MVT::v16i8: Opc = ARM::VZIPq8; break;
+    case MVT::v8i16: Opc = ARM::VZIPq16; break;
+    case MVT::v4f32:
+    case MVT::v4i32: Opc = ARM::VZIPq32; break;
+    }
+    return CurDAG->getTargetNode(Opc, dl, VT, VT,
                                  N->getOperand(0), N->getOperand(1));
   }
-  case ARMISD::VTRN16: {
+  case ARMISD::VUZP: {
+    unsigned Opc = 0;
     EVT VT = N->getValueType(0);
-    return CurDAG->getTargetNode(ARM::VTRNd16, dl, VT, VT,
+    switch (VT.getSimpleVT().SimpleTy) {
+    default: return NULL;
+    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
+    case MVT::v4i16: Opc = ARM::VUZPd16; break;
+    case MVT::v2f32:
+    case MVT::v2i32: Opc = ARM::VUZPd32; break;
+    case MVT::v16i8: Opc = ARM::VUZPq8; break;
+    case MVT::v8i16: Opc = ARM::VUZPq16; break;
+    case MVT::v4f32:
+    case MVT::v4i32: Opc = ARM::VUZPq32; break;
+    }
+    return CurDAG->getTargetNode(Opc, dl, VT, VT,
                                  N->getOperand(0), N->getOperand(1));
   }
-  case ARMISD::VTRN32: {
+  case ARMISD::VTRN: {
+    unsigned Opc = 0;
     EVT VT = N->getValueType(0);
-    return CurDAG->getTargetNode(ARM::VTRNq32, dl, VT, VT,
+    switch (VT.getSimpleVT().SimpleTy) {
+    default: return NULL;
+    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
+    case MVT::v4i16: Opc = ARM::VTRNd16; break;
+    case MVT::v2f32:
+    case MVT::v2i32: Opc = ARM::VTRNd32; break;
+    case MVT::v16i8: Opc = ARM::VTRNq8; break;
+    case MVT::v8i16: Opc = ARM::VTRNq16; break;
+    case MVT::v4f32:
+    case MVT::v4i32: Opc = ARM::VTRNq32; break;
+    }
+    return CurDAG->getTargetNode(Opc, dl, VT, VT,
                                  N->getOperand(0), N->getOperand(1));
   }
   }
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 18207c34a9..1c59cb01fa 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -493,15 +493,9 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case ARMISD::VREV64:        return "ARMISD::VREV64";
   case ARMISD::VREV32:        return "ARMISD::VREV32";
   case ARMISD::VREV16:        return "ARMISD::VREV16";
-  case ARMISD::VZIP32:        return "ARMISD::VZIP32";
-  case ARMISD::VZIP16:        return "ARMISD::VZIP16";
-  case ARMISD::VZIP8:         return "ARMISD::VZIP8";
-  case ARMISD::VUZP32:        return "ARMISD::VUZP32";
-  case ARMISD::VUZP16:        return "ARMISD::VUZP16";
-  case ARMISD::VUZP8:         return "ARMISD::VUZP8";
-  case ARMISD::VTRN32:        return "ARMISD::VTRN32";
-  case ARMISD::VTRN16:        return "ARMISD::VTRN16";
-  case ARMISD::VTRN8:         return "ARMISD::VTRN8";
+  case ARMISD::VZIP:          return "ARMISD::VZIP";
+  case ARMISD::VUZP:          return "ARMISD::VUZP";
+  case ARMISD::VTRN:          return "ARMISD::VTRN";
   }
 }
 
@@ -2566,7 +2560,7 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
   case OP_VDUP2:
   case OP_VDUP3:
     return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
-                       OpLHS, DAG.getConstant(OpNum-OP_VDUP0+1, MVT::i32));
+                       OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
   case OP_VEXT1:
   case OP_VEXT2:
   case OP_VEXT3:
@@ -2575,19 +2569,16 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
                        DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
   case OP_VUZPL:
   case OP_VUZPR:
-    return DAG.getNode(VT.is64BitVector() ? ARMISD::VUZP16 : ARMISD::VUZP32,
-                       dl, DAG.getVTList(VT, VT),
+    return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
                        OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
   case OP_VZIPL:
   case OP_VZIPR:
-    return DAG.getNode(VT.is64BitVector() ? ARMISD::VZIP16 : ARMISD::VZIP32,
-                       dl, DAG.getVTList(VT, VT),
+    return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
                        OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
   case OP_VTRNL:
   case OP_VTRNR:
-    return DAG.getNode(VT.is64BitVector() ? ARMISD::VTRN16 : ARMISD::VTRN32,
-                       dl, DAG.getVTList(VT, VT),
-                       OpLHS, OpRHS).getValue(0);
+    return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
+                       OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
   }
 }
 
diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index c54eddd88c..b2260e2d83 100644
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -133,15 +133,9 @@ namespace llvm {
       VREV32,       // reverse elements within 32-bit words
       VREV16,       // reverse elements within 16-bit halfwords
 
-      VZIP32,
-      VZIP16,
-      VZIP8,
-      VUZP32,
-      VUZP16,
-      VUZP8,
-      VTRN32,
-      VTRN16,
-      VTRN8
+      VZIP,         // zip
+      VUZP,         // unzip
+      VTRN          // transpose
     };
   }
 
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index b893c5859c..1a68dce637 100644
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -111,15 +111,9 @@ def NEONvrev16    : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
 
 def SDTARMVSHUF2  : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
                                          SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
-def NEONzip32     : SDNode<"ARMISD::VZIP32", SDTARMVSHUF2>;
-def NEONzip16     : SDNode<"ARMISD::VZIP16", SDTARMVSHUF2>;
-def NEONzip8      : SDNode<"ARMISD::VZIP8", SDTARMVSHUF2>;
-def NEONuzp32     : SDNode<"ARMISD::VUZP32", SDTARMVSHUF2>;
-def NEONuzp16     : SDNode<"ARMISD::VUZP16", SDTARMVSHUF2>;
-def NEONuzp8      : SDNode<"ARMISD::VUZP16", SDTARMVSHUF2>;
-def NEONtrn32     : SDNode<"ARMISD::VTRN32", SDTARMVSHUF2>;
-def NEONtrn16     : SDNode<"ARMISD::VTRN16", SDTARMVSHUF2>;
-def NEONtrn8      : SDNode<"ARMISD::VTRN8", SDTARMVSHUF2>;
+def NEONzip       : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
+def NEONuzp       : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
+def NEONtrn       : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
 
 //===----------------------------------------------------------------------===//
 // NEON operand definitions