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| author | Craig Topper <craig.topper@gmail.com> | 2012-01-22 03:07:48 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-01-22 03:07:48 +0000 |
| commit | 07a276277fe21f01c19e091b05402b69348e6b2d (patch) | |
| tree | 1da311d05675fa84e9fa6e2329126d63e37ad034 /lib | |
| parent | 69c96d71dd31401b2fbef5837e37cb81b2a7c83a (diff) | |
| download | llvm-07a276277fe21f01c19e091b05402b69348e6b2d.tar.gz llvm-07a276277fe21f01c19e091b05402b69348e6b2d.tar.bz2 llvm-07a276277fe21f01c19e091b05402b69348e6b2d.tar.xz | |
Make code a little less verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148651 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 9477dd5ade..83460a908f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -5052,11 +5052,10 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { if (ISD::isBuildVectorAllZeros(Op.getNode())) { // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. - if (Op.getValueType() == MVT::v4i32 || - Op.getValueType() == MVT::v8i32) + if (VT == MVT::v4i32 || VT == MVT::v8i32) return Op; - return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), + return getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), DAG, dl); } @@ -5064,11 +5063,10 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use // vpcmpeqd on 256-bit vectors. if (ISD::isBuildVectorAllOnes(Op.getNode())) { - if (Op.getValueType() == MVT::v4i32 || - (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2())) + if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) return Op; - return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl); + return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); } SDValue LD = isVectorBroadcast(Op, Subtarget); @@ -5137,7 +5135,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { DAG.getUNDEF(Item.getValueType()), &Mask[0]); } - return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); + return DAG.getNode(ISD::BITCAST, dl, VT, Item); } } |