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| author | Chad Rosier <mcrosier@apple.com> | 2011-11-08 00:03:32 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2011-11-08 00:03:32 +0000 |
| commit | 0eff39f2e25e9d8dd52b1eb7fa4e7cc6cc77875f (patch) | |
| tree | 4c1b735cc6c4946c2b97d03ab112fffdc4fdf6b0 /lib | |
| parent | 02e5fb0f5853aca232b134de8e8c88333a36d5c0 (diff) | |
| download | llvm-0eff39f2e25e9d8dd52b1eb7fa4e7cc6cc77875f.tar.gz llvm-0eff39f2e25e9d8dd52b1eb7fa4e7cc6cc77875f.tar.bz2 llvm-0eff39f2e25e9d8dd52b1eb7fa4e7cc6cc77875f.tar.xz | |
Enable support for returning i1, i8, and i16. Nothing special todo as it's the
callee's responsibility to sign or zero-extend the return value. The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144047 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMCallingConv.td | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 8 |
2 files changed, 9 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMCallingConv.td b/lib/Target/ARM/ARMCallingConv.td index a482a200aa..c22a08eec7 100644 --- a/lib/Target/ARM/ARMCallingConv.td +++ b/lib/Target/ARM/ARMCallingConv.td @@ -43,6 +43,7 @@ def CC_ARM_APCS : CallingConv<[ ]>; def RetCC_ARM_APCS : CallingConv<[ + CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, CCIfType<[f32], CCBitConvertToType<i32>>, // Handle all vector types as either f64 or v2f64. @@ -106,6 +107,7 @@ def CC_ARM_AAPCS_Common : CallingConv<[ ]>; def RetCC_ARM_AAPCS_Common : CallingConv<[ + CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> ]>; diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index c98156e886..8acdd91a19 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -1697,6 +1697,11 @@ bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, } else { assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); EVT CopyVT = RVLocs[0].getValVT(); + + // Special handling for extended integers. + if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16) + CopyVT = MVT::i32; + TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); unsigned ResultReg = createResultReg(DstRC); @@ -1913,7 +1918,8 @@ bool ARMFastISel::SelectCall(const Instruction *I) { MVT RetVT; if (RetTy->isVoidTy()) RetVT = MVT::isVoid; - else if (!isTypeLegal(RetTy, RetVT)) + else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 && + RetVT != MVT::i8 && RetVT != MVT::i1) return false; // TODO: For now if we have long calls specified we don't handle the call. |