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authorJohnny Chen <johnny.chen@apple.com>2011-04-05 00:16:18 +0000
committerJohnny Chen <johnny.chen@apple.com>2011-04-05 00:16:18 +0000
commit157536b1fb900e57efe042d48c7caeb87b1efd04 (patch)
treeb861e155cadcd26dcf931c9ed6daf6180e594d2f /lib
parent597028cc2840d9182523bd0179a1f95ddd931dae (diff)
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Fix SRS/SRSW encoding bits.
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with http://llvm.org/viewvc/llvm-project?view=rev&revision=128859. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td4
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index fabf95be77..a7bf4dc073 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1589,6 +1589,8 @@ def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
[/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111;
let Inst{22-20} = 0b110; // W = 1
+ let Inst{19-8} = 0xd05;
+ let Inst{7-5} = 0b000;
}
def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
@@ -1596,6 +1598,8 @@ def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
[/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111;
let Inst{22-20} = 0b100; // W = 0
+ let Inst{19-8} = 0xd05;
+ let Inst{7-5} = 0b000;
}
// Return From Exception is a system instruction -- for disassembly only