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author | Jim Grosbach <grosbach@apple.com> | 2011-08-05 16:11:38 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2011-08-05 16:11:38 +0000 |
commit | 16578b50889329eb62774148091ba0f38b681a09 (patch) | |
tree | 2d49e839366f9b1dd768d26ebe7827d10cd98963 /lib | |
parent | ca8c70b9536bf351ee92395dae6f99a59c011a3d (diff) | |
download | llvm-16578b50889329eb62774148091ba0f38b681a09.tar.gz llvm-16578b50889329eb62774148091ba0f38b681a09.tar.bz2 llvm-16578b50889329eb62774148091ba0f38b681a09.tar.xz |
ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 9 | ||||
-rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 10 | ||||
-rw-r--r-- | lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 3 | ||||
-rw-r--r-- | lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 3 |
4 files changed, 14 insertions, 11 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index dcc86957ad..6837d3622c 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -1093,8 +1093,7 @@ void ARMOperand::print(raw_ostream &OS) const { OS << ">"; break; case PostIndexRegister: - OS << "post-idx register " - << getAddrOpcStr(ARM_AM::getAM3Op(PostIdxReg.Imm)) + OS << "post-idx register " << (PostIdxReg.Imm ? "" : "-") << PostIdxReg.RegNum << ">"; break; @@ -1872,14 +1871,14 @@ parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { AsmToken Tok = Parser.getTok(); SMLoc S = Tok.getLoc(); bool haveEaten = false; - unsigned Imm = ARM_AM::getAM3Opc(ARM_AM::add, 0); + bool isAdd = true; int Reg = -1; if (Tok.is(AsmToken::Plus)) { Parser.Lex(); // Eat the '+' token. haveEaten = true; } else if (Tok.is(AsmToken::Minus)) { Parser.Lex(); // Eat the '-' token. - Imm = ARM_AM::getAM3Opc(ARM_AM::sub, 0); + isAdd = false; haveEaten = true; } if (Parser.getTok().is(AsmToken::Identifier)) @@ -1892,7 +1891,7 @@ parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { } SMLoc E = Parser.getTok().getLoc(); - Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, Imm, S, E)); + Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, S, E)); return MatchOperand_Success; } diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 26716763cf..d460ecd694 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1543,10 +1543,16 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, ++OpIdx; } else { // Disassemble the offset reg (Rm). - unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0); MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRm(insn)))); - MI.addOperand(MCOperand::CreateImm(Offset)); + // FIXME: Remove the 'else' once done w/ addrmode3 refactor. + if (Opcode == ARM::STRHTr || Opcode == ARM::LDRSBTr || + Opcode == ARM::LDRHTr || Opcode == ARM::LDRSHTr) + MI.addOperand(MCOperand::CreateImm(getUBit(insn))); + else { + unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0); + MI.addOperand(MCOperand::CreateImm(Offset)); + } OpIdx += 2; } diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 7972b27290..ef40699134 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -387,8 +387,7 @@ void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); - O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) - << getRegisterName(MO1.getReg()); + O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg()); } void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index c66941613c..2caf548f88 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -812,8 +812,7 @@ getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, // {3-0} Rm const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO1 = MI.getOperand(OpIdx+1); - unsigned Imm = MO1.getImm(); - bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; + bool isAdd = MO1.getImm() != 0; return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4); } |