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| author | Richard Osborne <richard@xmos.com> | 2013-01-25 21:25:12 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-25 21:25:12 +0000 |
| commit | 1f375e5bc78647f9b29564eafdc907250ccd91ed (patch) | |
| tree | 7f342d9a82414c36b7a5155d48808e3e8bfbf9db /lib | |
| parent | 0f1bcedf5a871c360f2ca1354464d81cb81bdca7 (diff) | |
| download | llvm-1f375e5bc78647f9b29564eafdc907250ccd91ed.tar.gz llvm-1f375e5bc78647f9b29564eafdc907250ccd91ed.tar.bz2 llvm-1f375e5bc78647f9b29564eafdc907250ccd91ed.tar.xz | |
Use the correct format in the STW / SETPSC instruction names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 14 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreRegisterInfo.cpp | 2 |
3 files changed, 9 insertions, 9 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index e785030c38..821c33da51 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -401,7 +401,7 @@ DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, fieldFromInstruction(Insn, 27, 5) << 4; switch (Opcode) { case 0x0c: - Inst.setOpcode(XCore::STW_3r); + Inst.setOpcode(XCore::STW_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x1c: Inst.setOpcode(XCore::XOR_l3r); diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 89845bc74d..b48a31d526 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -384,9 +384,9 @@ def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst), } let mayStore=1 in { -def STW_3r : _FL3R<0b000001100, (outs), - (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), - "stw $val, $addr[$offset]", []>; +def STW_l3r : _FL3R<0b000001100, (outs), + (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), + "stw $val, $addr[$offset]", []>; def STW_2rus : _F2RUS<0b0000, (outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), @@ -783,9 +783,9 @@ def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val), "setd res[$r], $val", [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; -def SETPSC_l2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2), - "setpsc res[$src1], $src2", - [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; +def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2), + "setpsc res[$src1], $src2", + [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r), "getst $dst, res[$r]", @@ -1006,7 +1006,7 @@ def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), - (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; + (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; def : Pat<(store GRRegs:$val, GRRegs:$addr), diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index e637d9a5be..7e3e4766a2 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -231,7 +231,7 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, .addReg(ScratchReg, RegState::Kill); break; case XCore::STWFI: - BuildMI(MBB, II, dl, TII.get(XCore::STW_3r)) + BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) .addReg(Reg, getKillRegState(isKill)) .addReg(FrameReg) .addReg(ScratchReg, RegState::Kill); |