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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-10 19:18:28 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-10 19:18:28 +0000 |
commit | 1f4772305adabd0e9390afad61e0b6a92ab8b830 (patch) | |
tree | 036c56f8ba0c1e14034de6478b0ec612a0a40734 /lib | |
parent | 69891c0115542d191a43023f60eca4e0dfd8dbcb (diff) | |
download | llvm-1f4772305adabd0e9390afad61e0b6a92ab8b830.tar.gz llvm-1f4772305adabd0e9390afad61e0b6a92ab8b830.tar.bz2 llvm-1f4772305adabd0e9390afad61e0b6a92ab8b830.tar.xz |
R600: Use BCNT_INT for evergreen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210569 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/R600/AMDGPUISelLowering.cpp | 8 | ||||
-rw-r--r-- | lib/Target/R600/AMDGPUSubtarget.h | 8 | ||||
-rw-r--r-- | lib/Target/R600/EvergreenInstructions.td | 2 | ||||
-rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 3 |
4 files changed, 16 insertions, 5 deletions
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp index 8ee453de35..83d80f0d5c 100644 --- a/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/lib/Target/R600/AMDGPUISelLowering.cpp @@ -220,9 +220,13 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); } + if (!Subtarget->hasBCNT(32)) + setOperationAction(ISD::CTPOP, MVT::i32, Expand); + + if (!Subtarget->hasBCNT(64)) + setOperationAction(ISD::CTPOP, MVT::i64, Expand); + for (MVT VT : { MVT::i32, MVT::i64 }) { - // TODO: Evergreen has BCNT_INT for CTPOP - setOperationAction(ISD::CTPOP, VT, Expand); setOperationAction(ISD::CTTZ, VT, Expand); setOperationAction(ISD::CTLZ, VT, Expand); } diff --git a/lib/Target/R600/AMDGPUSubtarget.h b/lib/Target/R600/AMDGPUSubtarget.h index b3b3a1a0ed..e1b5b3371f 100644 --- a/lib/Target/R600/AMDGPUSubtarget.h +++ b/lib/Target/R600/AMDGPUSubtarget.h @@ -80,6 +80,14 @@ public: return hasBFE(); } + bool hasBCNT(unsigned Size) const { + if (Size == 32) + return (getGeneration() >= EVERGREEN); + + assert(Size == 64); + return (getGeneration() >= SOUTHERN_ISLANDS); + } + bool hasMulU24() const { return (getGeneration() >= EVERGREEN); } diff --git a/lib/Target/R600/EvergreenInstructions.td b/lib/Target/R600/EvergreenInstructions.td index e09a0b2f78..0d0b9c751a 100644 --- a/lib/Target/R600/EvergreenInstructions.td +++ b/lib/Target/R600/EvergreenInstructions.td @@ -326,6 +326,8 @@ def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24", def DOT4_eg : DOT4_Common<0xBE>; defm CUBE_eg : CUBE_Common<0xC0>; +def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop>; + let hasSideEffects = 1 in { def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>; } diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index d05d71add8..608aad2d3c 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -211,9 +211,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : setOperationAction(ISD::FRINT, MVT::f64, Legal); } - setOperationAction(ISD::CTPOP, MVT::i32, Legal); - setOperationAction(ISD::CTPOP, MVT::i64, Legal); - setTargetDAGCombine(ISD::SELECT_CC); setTargetDAGCombine(ISD::SETCC); |