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author | Eric Christopher <echristo@apple.com> | 2010-08-24 01:10:04 +0000 |
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committer | Eric Christopher <echristo@apple.com> | 2010-08-24 01:10:04 +0000 |
commit | 2012c7bb7be28c163a4b8034e961ace51f6a7224 (patch) | |
tree | 2a1b6aa97daf23602e09db04b3c6feed2e08d727 /lib | |
parent | f06f309002f00e7927347502997f2df5756f4d9c (diff) | |
download | llvm-2012c7bb7be28c163a4b8034e961ace51f6a7224.tar.gz llvm-2012c7bb7be28c163a4b8034e961ace51f6a7224.tar.bz2 llvm-2012c7bb7be28c163a4b8034e961ace51f6a7224.tar.xz |
Fix the opcode and the operands for the load instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111885 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 2247b8549e..a1b9eb480c 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -415,10 +415,13 @@ bool ARMFastISel::ARMSelectLoad(const Instruction *I) { } // FIXME: There is more than one register class in the world... + // TODO: Verify the additions above work, otherwise we'll need to add the + // offset instead of 0 and do all sorts of operand munging. unsigned ResultReg = createResultReg(FixedRC); + unsigned Opc = AFI->isThumb2Function() ? ARM::tLDR : ARM::LDR; AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(ARM::LDR), ResultReg) - .addImm(0).addReg(Reg).addImm(Offset)); + TII.get(Opc), ResultReg) + .addReg(Reg).addReg(0).addImm(0)); UpdateValueMap(I, ResultReg); return true; |