[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR

 and not an MSA register

Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191684 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 26 insertions, 15 deletions

diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td
index 56678904db..430a09b9f0 100644
--- a/lib/Target/Mips/MipsMSAInstrFormats.td
+++ b/lib/Target/Mips/MipsMSAInstrFormats.td
@@ -45,6 +45,17 @@ class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
   let Inst{5-0} = minor;
 }
 
+class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
+  bits<5> rs;
+  bits<5> wd;
+
+  let Inst{25-18} = major;
+  let Inst{17-16} = df;
+  let Inst{15-11} = rs;
+  let Inst{10-6} = wd;
+  let Inst{5-0} = minor;
+}
+
 class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
   let Inst{25-18} = major;
   let Inst{17-16} = df;
diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td
index fdd924ece0..2a75e2b9e9 100644
--- a/lib/Target/Mips/MipsMSAInstrInfo.td
+++ b/lib/Target/Mips/MipsMSAInstrInfo.td
@@ -602,9 +602,9 @@ class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
 
-class FILL_B_ENC : MSA_2R_FMT<0b11000000, 0b00, 0b011110>;
-class FILL_H_ENC : MSA_2R_FMT<0b11000000, 0b01, 0b011110>;
-class FILL_W_ENC : MSA_2R_FMT<0b11000000, 0b10, 0b011110>;
+class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
+class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
+class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
 
 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
@@ -1148,13 +1148,13 @@ class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 }
 
 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
-                            SDPatternOperator OpNode, RegisterClass RCWD,
-                            RegisterClass RCWS = RCWD,
+                            SDPatternOperator OpNode, RegisterOperand ROWD,
+                            RegisterOperand ROWS = ROWD,
                             InstrItinClass itin = NoItinerary> {
-  dag OutOperandList = (outs RCWD:$wd);
-  dag InOperandList = (ins RCWS:$ws);
-  string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
-  list<dag> Pattern = [(set RCWD:$wd, (VT (OpNode RCWS:$ws)))];
+  dag OutOperandList = (outs ROWD:$wd);
+  dag InOperandList = (ins ROWS:$rs);
+  string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
+  list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROWS:$rs)))];
   InstrItinClass Itinerary = itin;
 }
 
@@ -1784,12 +1784,12 @@ class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
                                       MSA128DOpnd, MSA128WOpnd>;
 
-class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,  MSA128B,
-                                          GPR32>;
-class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, MSA128H,
-                                          GPR32>;
-class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, MSA128W,
-                                          GPR32>;
+class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
+                                          MSA128BOpnd, GPR32Opnd>;
+class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
+                                          MSA128HOpnd, GPR32Opnd>;
+class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
+                                          MSA128WOpnd, GPR32Opnd>;
 
 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;