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| author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-07-10 12:26:26 +0000 |
|---|---|---|
| committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-07-10 12:26:26 +0000 |
| commit | 296c1534b4ad835c6d9280145b63ca2b25831228 (patch) | |
| tree | 63a748e781378e37240e8276acd5b55f6063bd39 /lib | |
| parent | 2ec5933eae2e889225d33bd2f93a35926e958c95 (diff) | |
| download | llvm-296c1534b4ad835c6d9280145b63ca2b25831228.tar.gz llvm-296c1534b4ad835c6d9280145b63ca2b25831228.tar.bz2 llvm-296c1534b4ad835c6d9280145b63ca2b25831228.tar.xz | |
Reverting commit r185999 due to buildboot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186000 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Mips/MipsInstrFormats.td | 28 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 21 |
2 files changed, 0 insertions, 49 deletions
diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index 6073476af2..14cfcf96d3 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -491,34 +491,6 @@ class TEQ_FM<bits<6> funct> { } //===----------------------------------------------------------------------===// -// System calls format <op|code_|funct> -//===----------------------------------------------------------------------===// - -class SYS_FM<bits<6> funct> -{ - bits<20> code_; - bits<32> Inst; - let Inst{31-26} = 0x0; - let Inst{25-6} = code_; - let Inst{5-0} = funct; -} - -//===----------------------------------------------------------------------===// -// Break instruction format <op|code_1|funct> -//===----------------------------------------------------------------------===// - -class BRK_FM<bits<6> funct> -{ - bits<10> code_1; - bits<10> code_2; - bits<32> Inst; - let Inst{31-26} = 0x0; - let Inst{25-16} = code_1; - let Inst{15-6} = code_2; - let Inst{5-0} = funct; -} - -//===----------------------------------------------------------------------===// // // FLOATING POINT INSTRUCTION FORMATS // diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 712e204427..d2164f7263 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -250,12 +250,6 @@ def simm16 : Operand<i32> { def simm20 : Operand<i32> { } -def uimm20 : Operand<i32> { -} - -def uimm10 : Operand<i32> { -} - def simm16_64 : Operand<i64>; def shamt : Operand<i32>; @@ -643,14 +637,6 @@ class BAL_FT : let hasDelaySlot = 1; let Defs = [RA]; } -// Syscall -class SYS_FT<string opstr> : - InstSE<(outs), (ins uimm20:$code_), - !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>; -// Break -class BRK_FT<string opstr> : - InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), - !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>; // Sync let hasSideEffects = 1 in @@ -955,9 +941,6 @@ defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; def SYNC : SYNC_FT, SYNC_FM; def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TEQ_FM<0x34>; -def BREAK : BRK_FT<"break">, BRK_FM<0xd>; -def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>; - /// Load-linked, Store-conditional let Predicates = [NotN64, HasStdEnc] in { def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; @@ -1136,10 +1119,6 @@ def : InstAlias<"bnez $rs,$offset", def : InstAlias<"beqz $rs,$offset", (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>, Requires<[NotMips64]>; -def : InstAlias<"syscall", (SYSCALL 0), 1>; - -def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; -def : InstAlias<"break", (BREAK 0, 0), 1>; //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions //===----------------------------------------------------------------------===// |