Specify instruction encoding using range list to avoid endianess issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56276 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 26 insertions, 25 deletions

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index eae947e481..df3dc93252 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -142,21 +142,21 @@ class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
       asm,"",pattern> {
   let Inst{24}    = 1; // L bit
-  let Inst{25-27} = 5;
+  let Inst{25-27} = {1,0,1};
 }
 class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
           list<dag> pattern>
   : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
        "", pattern> {
   let Inst{24}    = 1; // L bit
-  let Inst{25-27} = 5;
+  let Inst{25-27} = {1,0,1};
 }
 class ABLXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
           list<dag> pattern>
   : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
        "", pattern> {
-  let Inst{4-7}   = 3;
-  let Inst{20-27} = 0x12;
+  let Inst{4-7}   = {1,1,0,0};
+  let Inst{20-27} = {0,1,0,0,1,0,0,0};
 }
 // FIXME: BX
 class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
@@ -168,14 +168,14 @@ class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
   : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
        "", pattern> {
   let Inst{24}    = 0; // L bit
-  let Inst{25-27} = 5;
+  let Inst{25-27} = {1,0,1};
 }
 class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
          string asm, list<dag> pattern>
   : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
       asm,"",pattern> {
   let Inst{24}    = 0; // L bit
-  let Inst{25-27} = 5;
+  let Inst{25-27} = {1,0,1};
 }
 
 // BR_JT instructions
@@ -184,25 +184,26 @@ class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
   : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
        asm, "", pattern> {
   let Inst{20}    = 0; // S Bit
-  let Inst{21-24} = 0xd;
-  let Inst{26-27} = 0;
+  let Inst{21-24} = {1,0,1,1};
+  let Inst{26-27} = {0,0};
 }
-// == ldr pc
+// == add pc
 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
   : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
        asm, "", pattern> {
-  let Inst{20}    = 1; // L bit
-  let Inst{21}    = 0; // W bit
-  let Inst{22}    = 0; // B bit
-  let Inst{24}    = 1; // P bit
+  let Inst{20}    = 0; // S bit
+  let Inst{21-24} = {0,0,1,0};
+  let Inst{26-27} = {0,0};
 }
-// == add pc
+// == ldr pc
 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
   : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
        asm, "", pattern> {
-  let Inst{20}    = 0; // S bit
-  let Inst{21-24} = 4;
-  let Inst{26-27} = 0;
+  let Inst{20}    = 1; // L bit
+  let Inst{21}    = 0; // W bit
+  let Inst{22}    = 0; // B bit
+  let Inst{24}    = 1; // P bit
+  let Inst{26-27} = {0,0};
 }
 
 
@@ -212,21 +213,21 @@ class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{21-24} = opcod;
-  let Inst{26-27} = 0;
+  let Inst{26-27} = {0,0};
 }
 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
            string asm, list<dag> pattern>
   : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
        asm, "", pattern> {
   let Inst{21-24} = opcod;
-  let Inst{26-27} = 0;
+  let Inst{26-27} = {0,0};
 }
 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
   : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
        "", pattern> {
   let Inst{21-24} = opcod;
-  let Inst{26-27} = 0;
+  let Inst{26-27} = {0,0};
 }
 class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
             string asm, list<dag> pattern>
@@ -239,7 +240,7 @@ class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
   : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
-  let Inst{26-27} = 1;
+  let Inst{26-27} = {1,0};
 }
 class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
@@ -642,7 +643,7 @@ class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
   : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
-  let Inst{25-27} = 0x4;
+  let Inst{25-27} = {0,0,1};
 }
 class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
@@ -650,7 +651,7 @@ class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm,
        "", pattern> {
   let Inst{20}    = 1; // L bit
   let Inst{22}    = 0; // S bit
-  let Inst{25-27} = 0x4;
+  let Inst{25-27} = {0,0,1};
 }
 class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
@@ -658,7 +659,7 @@ class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm,
        "", pattern> {
   let Inst{20}    = 1; // L bit
   let Inst{22}    = 1; // S bit
-  let Inst{25-27} = 0x4;
+  let Inst{25-27} = {0,0,1};
 }
 class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
@@ -666,7 +667,7 @@ class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
        "", pattern> {
   let Inst{20}    = 0; // L bit
   let Inst{22}    = 0; // S bit
-  let Inst{25-27} = 0x4;
+  let Inst{25-27} = {0,0,1};
 }