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authorJohnny Chen <johnny.chen@apple.com>2011-04-05 23:28:00 +0000
committerJohnny Chen <johnny.chen@apple.com>2011-04-05 23:28:00 +0000
commit2c868d1eef1e52a2b3211050006344e00c461ac3 (patch)
tree16ac935d7c2ec9fc0a5a80d4367d3c317fa69a46 /lib
parente4dc1966baf6b2b5b27c50dd0321852666788588 (diff)
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Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp8
1 files changed, 7 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 58f9c1f759..8c89505a20 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -1474,6 +1474,12 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
+ // Sanity check the registers, which should not be 15.
+ if (decodeRd(insn) == 15 || decodeRm(insn) == 15)
+ return false;
+ if (ThreeReg && decodeRn(insn) == 15)
+ return false;
+
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRd(insn))));
++OpIdx;
@@ -1498,7 +1504,7 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
ARM_AM::ShiftOpc Opc = ARM_AM::no_shift;
if (Opcode == ARM::PKHBT)
Opc = ARM_AM::lsl;
- else if (Opcode == ARM::PKHBT)
+ else if (Opcode == ARM::PKHTB)
Opc = ARM_AM::asr;
getImmShiftSE(Opc, ShiftAmt);
MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt)));