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| author | Michael Liao <michael.liao@intel.com> | 2013-06-21 18:45:27 +0000 |
|---|---|---|
| committer | Michael Liao <michael.liao@intel.com> | 2013-06-21 18:45:27 +0000 |
| commit | 2da863984bdd0123fa53ab3f5439d239a5a9e419 (patch) | |
| tree | c08d34b73b0f773b443622305abc4e274f1f667e /lib | |
| parent | c12c880998a0be9de2d20f7855029ef743570a06 (diff) | |
| download | llvm-2da863984bdd0123fa53ab3f5439d239a5a9e419.tar.gz llvm-2da863984bdd0123fa53ab3f5439d239a5a9e419.tar.bz2 llvm-2da863984bdd0123fa53ab3f5439d239a5a9e419.tar.xz | |
Fix PR16360
When (srl (anyextend x), c) is folded into (anyextend (srl x, c)), the
high bits are not cleared. Add 'and' to clear off them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184575 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index f650b4d88a..cb9778bbd6 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3915,8 +3915,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) { DAG.getConstant(~0ULL >> ShAmt, VT)); } - - // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) + // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask) if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { // Shifting in all undef bits? EVT SmallVT = N0.getOperand(0).getValueType(); @@ -3929,7 +3928,10 @@ SDValue DAGCombiner::visitSRL(SDNode *N) { N0.getOperand(0), DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); AddToWorkList(SmallShift.getNode()); - return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift); + APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()).lshr(ShiftAmt); + return DAG.getNode(ISD::AND, SDLoc(N), VT, + DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift), + DAG.getConstant(Mask, VT)); } } |