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| author | Lauro Ramos Venancio <lauro.venancio@gmail.com> | 2006-12-28 13:11:14 +0000 |
|---|---|---|
| committer | Lauro Ramos Venancio <lauro.venancio@gmail.com> | 2006-12-28 13:11:14 +0000 |
| commit | 301009a0fca8dea601d54954eaaa8fae1e055c75 (patch) | |
| tree | 67c1b06901f425aa9d3316d5962f7baf53a63714 /lib | |
| parent | 6547c5598855837c5ca830aff4e3b48eb17e1f21 (diff) | |
| download | llvm-301009a0fca8dea601d54954eaaa8fae1e055c75.tar.gz llvm-301009a0fca8dea601d54954eaaa8fae1e055c75.tar.bz2 llvm-301009a0fca8dea601d54954eaaa8fae1e055c75.tar.xz | |
Implement SELECT_CC (f32/f64) for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32762 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 14 |
2 files changed, 16 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index fadeb2a09c..d0ad39fbc7 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -73,6 +73,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setOperationAction(ISD::SETCC, MVT::f64, Expand); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); + setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); + setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); setOperationAction(ISD::MEMSET, MVT::Other, Expand); @@ -745,7 +747,7 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { SDOperand Cmp; SDOperand ARMCC; LowerCMP(Cmp, ARMCC, LHS, RHS, CC, DAG); - return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp); + return DAG.getNode(ARMISD::SELECT, Op.getValueType(), TrueVal, FalseVal, ARMCC, Cmp); } static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) { diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 86e233aa19..b13a265344 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -102,7 +102,7 @@ def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet, [SDNPHasChain, SDNPOptInFlag]>; -def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>; +def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]>; def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>; def SDTarmfmstat : SDTypeProfile<0, 0, []>; @@ -209,6 +209,18 @@ let isTwoAddress = 1 in { "mov$cc $dst, $true", [(set IntRegs:$dst, (armselect addr_mode1:$true, IntRegs:$false, imm:$cc))]>; + + def fcpyscond : InstARM<(ops FPRegs:$dst, FPRegs:$false, + FPRegs:$true, CCOp:$cc), + "fcpys$cc $dst, $true", + [(set FPRegs:$dst, (armselect FPRegs:$true, + FPRegs:$false, imm:$cc))]>; + + def fcpydcond : InstARM<(ops DFPRegs:$dst, DFPRegs:$false, + DFPRegs:$true, CCOp:$cc), + "fcpyd$cc $dst, $true", + [(set DFPRegs:$dst, (armselect DFPRegs:$true, + DFPRegs:$false, imm:$cc))]>; } def MUL : IntBinOp<"mul", mul>; |