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| author | Craig Topper <craig.topper@gmail.com> | 2011-12-29 03:09:33 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2011-12-29 03:09:33 +0000 |
| commit | 3224e6b60a82eedf703c8c4a628362e8095aed01 (patch) | |
| tree | 100674b17295cd685969f6fc0b80b697a25b2bb6 /lib | |
| parent | 3a023d318075639434fdb5e2424d0c2c5edd89e7 (diff) | |
| download | llvm-3224e6b60a82eedf703c8c4a628362e8095aed01.tar.gz llvm-3224e6b60a82eedf703c8c4a628362e8095aed01.tar.bz2 llvm-3224e6b60a82eedf703c8c4a628362e8095aed01.tar.xz | |
Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147335 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 28cd252ce8..8382fbde7f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -5166,13 +5166,13 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || (ExtVT == MVT::i64 && Subtarget->is64Bit())) { if (VT.getSizeInBits() == 256) { - EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); - SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); + SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), DAG, dl); } + assert (VT.getSizeInBits() == 128 && "Expected an SSE value type!"); Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(), @@ -5180,16 +5180,14 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); if (VT.getSizeInBits() == 256) { - EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); - SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); + SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), DAG, dl); } - assert (VT.getSizeInBits() == 128 || "Expected an SSE value type!"); - EVT MiddleVT = MVT::v4i32; - Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); + assert (VT.getSizeInBits() == 128 && "Expected an SSE value type!"); + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasXMMInt(), DAG); return DAG.getNode(ISD::BITCAST, dl, VT, Item); |