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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-01-13 16:51:00 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-01-13 16:51:00 +0000 |
| commit | 36713c2c0a9e4aeebe4cae4ef5efbc13d4103850 (patch) | |
| tree | ebd86331fcbc1cbee3176eb060d38d114af44f77 /lib | |
| parent | 286cc1354606638fef69eee80e98dadb90406e51 (diff) | |
| download | llvm-36713c2c0a9e4aeebe4cae4ef5efbc13d4103850.tar.gz llvm-36713c2c0a9e4aeebe4cae4ef5efbc13d4103850.tar.bz2 llvm-36713c2c0a9e4aeebe4cae4ef5efbc13d4103850.tar.xz | |
[AArch64] Fix assertion failure caused by an invalid comparison between APInt values.
APInt only knows how to compare values with the same BitWidth and asserts
in all other cases.
With this fix, function PerformORCombine does not use the APInt equality
operator if the APInt values returned by 'isConstantSplat' differ in BitWidth.
In that case they are different and no comparison is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199119 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index ce9ce3aeb5..317a41a05f 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -3476,8 +3476,9 @@ static SDValue PerformORCombine(SDNode *N, BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1)); APInt SplatBits1; if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize, - HasAnyUndefs) && - !HasAnyUndefs && SplatBits0 == ~SplatBits1) { + HasAnyUndefs) && !HasAnyUndefs && + SplatBits0.getBitWidth() == SplatBits1.getBitWidth() && + SplatBits0 == ~SplatBits1) { return DAG.getNode(ISD::VSELECT, DL, VT, N0->getOperand(1), N0->getOperand(0), N1->getOperand(0)); |