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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-07-11 07:31:03 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-07-11 07:31:03 +0000 |
| commit | 377b7b7ca3a28e2329abd1f22b9bc0482635ccce (patch) | |
| tree | e87be6114dca1b26505393104d4c12076d76ce12 /lib | |
| parent | 27689b0affee8fb1bfbef11dcc84287b7757cfe8 (diff) | |
| download | llvm-377b7b7ca3a28e2329abd1f22b9bc0482635ccce.tar.gz llvm-377b7b7ca3a28e2329abd1f22b9bc0482635ccce.tar.bz2 llvm-377b7b7ca3a28e2329abd1f22b9bc0482635ccce.tar.xz | |
Replace copyRegToReg with copyPhysReg for CellSPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108084 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.cpp | 34 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.h | 10 |
2 files changed, 10 insertions, 34 deletions
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 9dfe01476c..177f1bc857 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -249,40 +249,18 @@ SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI, return 0; } -bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC, - DebugLoc DL) const +void SPUInstrInfo::copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, DebugLoc DL, + unsigned DestReg, unsigned SrcReg, + bool KillSrc) const { // We support cross register class moves for our aliases, such as R3 in any // reg class to any other reg class containing R3. This is required because // we instruction select bitconvert i64 -> f64 as a noop for example, so our // types have no specific meaning. - if (DestRC == SPU::R8CRegisterClass) { - BuildMI(MBB, MI, DL, get(SPU::LRr8), DestReg).addReg(SrcReg); - } else if (DestRC == SPU::R16CRegisterClass) { - BuildMI(MBB, MI, DL, get(SPU::LRr16), DestReg).addReg(SrcReg); - } else if (DestRC == SPU::R32CRegisterClass) { - BuildMI(MBB, MI, DL, get(SPU::LRr32), DestReg).addReg(SrcReg); - } else if (DestRC == SPU::R32FPRegisterClass) { - BuildMI(MBB, MI, DL, get(SPU::LRf32), DestReg).addReg(SrcReg); - } else if (DestRC == SPU::R64CRegisterClass) { - BuildMI(MBB, MI, DL, get(SPU::LRr64), DestReg).addReg(SrcReg); - } else if (DestRC == SPU::R64FPRegisterClass) { - BuildMI(MBB, MI, DL, get(SPU::LRf64), DestReg).addReg(SrcReg); - } else if (DestRC == SPU::GPRCRegisterClass) { - BuildMI(MBB, MI, DL, get(SPU::LRr128), DestReg).addReg(SrcReg); - } else if (DestRC == SPU::VECREGRegisterClass) { - BuildMI(MBB, MI, DL, get(SPU::LRv16i8), DestReg).addReg(SrcReg); - } else { - // Attempt to copy unknown/unsupported register class! - return false; - } - - return true; + BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); } void diff --git a/lib/Target/CellSPU/SPUInstrInfo.h b/lib/Target/CellSPU/SPUInstrInfo.h index 0a914865af..baaac7ec1a 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.h +++ b/lib/Target/CellSPU/SPUInstrInfo.h @@ -56,12 +56,10 @@ namespace llvm { unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; - virtual bool copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC, - DebugLoc DL) const; + virtual void copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, DebugLoc DL, + unsigned DestReg, unsigned SrcReg, + bool KillSrc) const; //! Store a register to a stack slot, based on its register class. virtual void storeRegToStackSlot(MachineBasicBlock &MBB, |