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| author | Stepan Dyatkovskiy <stpworld@narod.ru> | 2014-04-03 11:29:15 +0000 |
|---|---|---|
| committer | Stepan Dyatkovskiy <stpworld@narod.ru> | 2014-04-03 11:29:15 +0000 |
| commit | 37e5cfa4aae0dd693ab0c35ff78d37f5ddfe177d (patch) | |
| tree | b8f393497bcc07da41faf2778697ccc041520ac8 /lib | |
| parent | 3f11cd0d25971e2f8231a74a27339146d786644d (diff) | |
| download | llvm-37e5cfa4aae0dd693ab0c35ff78d37f5ddfe177d.tar.gz llvm-37e5cfa4aae0dd693ab0c35ff78d37f5ddfe177d.tar.bz2 llvm-37e5cfa4aae0dd693ab0c35ff78d37f5ddfe177d.tar.xz | |
PR19320:
The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP.
It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 8372f05c59..9c57a244fd 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5408,11 +5408,16 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, Operands.size() == 4) { ARMOperand *Op = static_cast<ARMOperand *>(Operands[2]); assert(Op->isReg() && "expected register argument"); - assert(MRI->getMatchingSuperReg(Op->getReg(), ARM::gsub_0, - &MRI->getRegClass(ARM::GPRPairRegClassID)) - && "expected register pair"); + + unsigned SuperReg = MRI->getMatchingSuperReg( + Op->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID)); + + assert(SuperReg && "expected register pair"); + + unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1); + Operands.insert(Operands.begin() + 3, - ARMOperand::CreateReg(Op->getReg() + 1, Op->getStartLoc(), + ARMOperand::CreateReg(PairedReg, Op->getStartLoc(), Op->getEndLoc())); } |